Simulation Results: edn

 
04/01/2026 00:13:51 sha: 05ff44d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.43 %
  • code
  • 95.83 %
  • assert
  • 97.61 %
  • func
  • 92.86 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.14 %
  • toggle
  • 97.12 %
  • FSM
  • 92.47 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.290s 24.715us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.340s 56.399us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.230s 16.537us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.420s 3348.638us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.550s 103.782us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.860s 122.630us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.230s 16.537us 20 20 100.00
edn_csr_aliasing 1.550s 103.782us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 178.670s 24308.335us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 178.670s 24308.335us 300 300 100.00
genbits 300 300 100.00
edn_genbits 178.670s 24308.335us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.290s 21.858us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.630s 153.900us 200 200 100.00
errs 100 100 100.00
edn_err 1.670s 28.479us 100 100 100.00
disable 100 100 100.00
edn_disable 1.290s 14.173us 50 50 100.00
edn_disable_auto_req_mode 1.450s 168.993us 50 50 100.00
stress_all 50 50 100.00
edn_stress_all 4.880s 332.594us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.280s 14.403us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.460s 65.963us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.240s 604.954us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.240s 604.954us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.340s 56.399us 5 5 100.00
edn_csr_rw 1.230s 16.537us 20 20 100.00
edn_csr_aliasing 1.550s 103.782us 5 5 100.00
edn_same_csr_outstanding 1.510s 223.194us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.340s 56.399us 5 5 100.00
edn_csr_rw 1.230s 16.537us 20 20 100.00
edn_csr_aliasing 1.550s 103.782us 5 5 100.00
edn_same_csr_outstanding 1.510s 223.194us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 6.870s 580.178us 5 5 100.00
edn_tl_intg_err 3.010s 1000.680us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.060s 19.249us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.630s 153.900us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 6.870s 580.178us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 6.870s 580.178us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 6.870s 580.178us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 6.870s 580.178us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.630s 153.900us 200 200 100.00
edn_sec_cm 6.870s 580.178us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.630s 153.900us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 3.010s 1000.680us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
edn_stress_all_with_rand_reset 101.490s 12404.944us 50 50 100.00

Error Messages

   Test seed line log context