flash_ctrl Simulation Results

Simulation Results: flash_ctrl

04/01/2026 00:13:51 sha: 05ff44d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
97.00 %

code
95.90 %

assert
96.71 %

func
98.39 %

line
96.09 %

branch
97.41 %

cond
94.81 %

toggle
98.66 %

FSM
92.52 %

Validation stages

V1		100.00%
V2		98.94%
V2S		99.64%
V3		100.00%
unmapped		100.00%

145/145 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	flash_ctrl_smoke	131.890s	146.519us	50	50	100.00
smoke_hw				5	5	100.00
	flash_ctrl_smoke_hw	24.740s	18.243us	5	5	100.00
csr_hw_reset				5	5	100.00
	flash_ctrl_csr_hw_reset	42.470s	46.657us	5	5	100.00
csr_rw				20	20	100.00
	flash_ctrl_csr_rw	16.230s	49.227us	20	20	100.00
csr_bit_bash				5	5	100.00
	flash_ctrl_csr_bit_bash	45.590s	2833.412us	5	5	100.00
csr_aliasing				5	5	100.00
	flash_ctrl_csr_aliasing	43.860s	10186.077us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	flash_ctrl_csr_mem_rw_with_rand_reset	19.030s	173.070us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	flash_ctrl_csr_rw	16.230s	49.227us	20	20	100.00
	flash_ctrl_csr_aliasing	43.860s	10186.077us	5	5	100.00
mem_walk				5	5	100.00
	flash_ctrl_mem_walk	12.350s	28.580us	5	5	100.00
mem_partial_access				5	5	100.00
	flash_ctrl_mem_partial_access	12.400s	49.055us	5	5	100.00

1124/1136 passed

98.94 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sw_op				5	5	100.00
	flash_ctrl_sw_op	22.290s	70.352us	5	5	100.00
host_read_direct				5	5	100.00
	flash_ctrl_host_dir_rd	78.940s	227.193us	5	5	100.00
rma_hw_if				43	43	100.00
	flash_ctrl_hw_rma	1577.640s	571662.319us	3	3	100.00
	flash_ctrl_hw_rma_reset	1101.840s	540456.402us	20	20	100.00
	flash_ctrl_lcmgr_intg	12.940s	62.739us	20	20	100.00
host_controller_arb				5	5	100.00
	flash_ctrl_host_ctrl_arb	2034.310s	245526.004us	5	5	100.00
erase_suspend				5	5	100.00
	flash_ctrl_erase_suspend	298.450s	4177.913us	5	5	100.00
program_reset				30	30	100.00
	flash_ctrl_prog_reset	186.000s	6100.310us	30	30	100.00
full_memory_access				5	5	100.00
	flash_ctrl_full_mem_access	3015.240s	50872.241us	5	5	100.00
rd_buff_eviction				5	5	100.00
	flash_ctrl_rd_buff_evict	102.020s	706.851us	5	5	100.00
rd_buff_eviction_w_ecc				96	100	96.00
	flash_ctrl_rw_evict	30.080s	86.381us	38	40	95.00
	flash_ctrl_rw_evict_all_en	32.020s	42.082us	38	40	95.00
	flash_ctrl_re_evict	33.980s	151.145us	20	20	100.00
host_arb				20	20	100.00
	flash_ctrl_phy_arb	245.680s	2894.779us	20	20	100.00
host_interleave				20	20	100.00
	flash_ctrl_phy_arb	245.680s	2894.779us	20	20	100.00
memory_protection				20	20	100.00
	flash_ctrl_mp_regions	774.230s	17666.549us	20	20	100.00
fetch_code				10	10	100.00
	flash_ctrl_fetch_code	27.820s	404.121us	10	10	100.00
all_partitions				20	20	100.00
	flash_ctrl_rand_ops	755.200s	3059.244us	20	20	100.00
error_mp				10	10	100.00
	flash_ctrl_error_mp	718.680s	4963.755us	10	10	100.00
error_prog_win				10	10	100.00
	flash_ctrl_error_prog_win	683.780s	1723.153us	10	10	100.00
error_prog_type				5	5	100.00
	flash_ctrl_error_prog_type	1576.620s	10357.470us	5	5	100.00
error_read_seed				20	20	100.00
	flash_ctrl_hw_read_seed_err	13.660s	23.512us	20	20	100.00
read_write_overflow				5	5	100.00
	flash_ctrl_oversize_error	171.350s	3017.730us	5	5	100.00
flash_ctrl_disable				50	50	100.00
	flash_ctrl_disable	22.010s	21.922us	50	50	100.00
flash_ctrl_connect				80	80	100.00
	flash_ctrl_connect	17.190s	19.562us	80	80	100.00
stress_all				5	5	100.00
	flash_ctrl_stress_all	528.500s	892.891us	5	5	100.00
secret_partition				130	130	100.00
	flash_ctrl_hw_sec_otp	237.900s	41413.756us	50	50	100.00
	flash_ctrl_otp_reset	130.200s	135.028us	80	80	100.00
isolation_partition				3	3	100.00
	flash_ctrl_hw_rma	1577.640s	571662.319us	3	3	100.00
interrupts				96	100	96.00
	flash_ctrl_intr_rd	226.070s	2407.626us	38	40	95.00
	flash_ctrl_intr_wr	78.390s	4651.048us	9	10	90.00
	flash_ctrl_intr_rd_slow_flash	342.800s	37233.975us	40	40	100.00
	flash_ctrl_intr_wr_slow_flash	307.130s	64351.518us	9	10	90.00
invalid_op				20	20	100.00
	flash_ctrl_invalid_op	68.990s	3290.546us	20	20	100.00
mid_op_rst				5	5	100.00
	flash_ctrl_mid_op_rst	74.250s	1720.126us	5	5	100.00
double_bit_err				34	35	97.14
	flash_ctrl_read_word_sweep_derr	19.390s	316.238us	5	5	100.00
	flash_ctrl_ro_derr	125.260s	1463.843us	10	10	100.00
	flash_ctrl_rw_derr	214.430s	17752.691us	10	10	100.00
	flash_ctrl_derr_detect	169.860s	820.668us	5	5	100.00
	flash_ctrl_integrity	476.450s	9456.217us	4	5	80.00
single_bit_err				25	25	100.00
	flash_ctrl_read_word_sweep_serr	21.730s	25.476us	5	5	100.00
	flash_ctrl_ro_serr	136.010s	3034.739us	10	10	100.00
	flash_ctrl_rw_serr	194.220s	5259.713us	10	10	100.00
singlebit_err_counter				5	5	100.00
	flash_ctrl_serr_counter	80.760s	1656.046us	5	5	100.00
singlebit_err_address				5	5	100.00
	flash_ctrl_serr_address	102.230s	3617.714us	5	5	100.00
scramble				59	62	95.16
	flash_ctrl_wo	230.890s	3154.015us	19	20	95.00
	flash_ctrl_write_word_sweep	14.220s	41.555us	1	1	100.00
	flash_ctrl_read_word_sweep	6.360s	26.668us	1	1	100.00
	flash_ctrl_ro	107.550s	2738.108us	19	20	95.00
	flash_ctrl_rw	498.240s	4165.012us	19	20	95.00
filesystem_support				5	5	100.00
	flash_ctrl_fs_sup	42.020s	2398.511us	5	5	100.00
rma_write_process_error				23	23	100.00
	flash_ctrl_rma_err	1040.650s	66793.956us	3	3	100.00
	flash_ctrl_hw_prog_rma_wipe_err	248.690s	10019.909us	20	20	100.00
alert_test				50	50	100.00
	flash_ctrl_alert_test	14.430s	52.982us	50	50	100.00
intr_test				50	50	100.00
	flash_ctrl_intr_test	12.350s	51.998us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	flash_ctrl_tl_errors	17.950s	220.526us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	flash_ctrl_tl_errors	17.950s	220.526us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	flash_ctrl_csr_hw_reset	42.470s	46.657us	5	5	100.00
	flash_ctrl_csr_rw	16.230s	49.227us	20	20	100.00
	flash_ctrl_csr_aliasing	43.860s	10186.077us	5	5	100.00
	flash_ctrl_same_csr_outstanding	33.110s	152.019us	20	20	100.00
tl_d_partial_access				50	50	100.00
	flash_ctrl_csr_hw_reset	42.470s	46.657us	5	5	100.00
	flash_ctrl_csr_rw	16.230s	49.227us	20	20	100.00
	flash_ctrl_csr_aliasing	43.860s	10186.077us	5	5	100.00
	flash_ctrl_same_csr_outstanding	33.110s	152.019us	20	20	100.00

V2S

820/823 passed

99.64 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	73.100s	169.488us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	flash_ctrl_shadow_reg_errors	73.100s	169.488us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	73.100s	169.488us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	flash_ctrl_shadow_reg_errors	73.100s	169.488us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	flash_ctrl_shadow_reg_errors_with_csr_rw	60.270s	520.377us	20	20	100.00
tl_intg_err				25	25	100.00
	flash_ctrl_tl_intg_err	543.910s	1442.885us	20	20	100.00
	flash_ctrl_sec_cm	2178.350s	3473.675us	5	5	100.00
sec_cm_reg_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	543.910s	1442.885us	20	20	100.00
sec_cm_host_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	543.910s	1442.885us	20	20	100.00
sec_cm_mem_bus_integrity				6	6	100.00
	flash_ctrl_rd_intg	33.140s	208.062us	3	3	100.00
	flash_ctrl_wr_intg	13.560s	201.754us	3	3	100.00
sec_cm_scramble_key_sideload				50	50	100.00
	flash_ctrl_smoke	131.890s	146.519us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				260	260	100.00
	flash_ctrl_otp_reset	130.200s	135.028us	80	80	100.00
	flash_ctrl_disable	22.010s	21.922us	50	50	100.00
	flash_ctrl_sec_info_access	73.390s	23408.998us	50	50	100.00
	flash_ctrl_connect	17.190s	19.562us	80	80	100.00
sec_cm_ctrl_config_regwen				5	5	100.00
	flash_ctrl_config_regwen	12.930s	37.838us	5	5	100.00
sec_cm_data_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	16.230s	49.227us	20	20	100.00
sec_cm_data_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	73.100s	169.488us	20	20	100.00
sec_cm_info_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	16.230s	49.227us	20	20	100.00
sec_cm_info_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	73.100s	169.488us	20	20	100.00
sec_cm_bank_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	16.230s	49.227us	20	20	100.00
sec_cm_bank_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	73.100s	169.488us	20	20	100.00
sec_cm_mem_ctrl_global_esc				50	50	100.00
	flash_ctrl_disable	22.010s	21.922us	50	50	100.00
sec_cm_mem_ctrl_local_esc				6	6	100.00
	flash_ctrl_rd_intg	33.140s	208.062us	3	3	100.00
	flash_ctrl_access_after_disable	12.080s	69.803us	3	3	100.00
sec_cm_mem_addr_infection				3	3	100.00
	flash_ctrl_host_addr_infection	29.170s	44.522us	3	3	100.00
sec_cm_mem_disable_config_mubi				50	50	100.00
	flash_ctrl_disable	22.010s	21.922us	50	50	100.00
sec_cm_exec_config_redun				10	10	100.00
	flash_ctrl_fetch_code	27.820s	404.121us	10	10	100.00
sec_cm_mem_scramble				19	20	95.00
	flash_ctrl_rw	498.240s	4165.012us	19	20	95.00
sec_cm_mem_integrity				24	25	96.00
	flash_ctrl_rw_serr	194.220s	5259.713us	10	10	100.00
	flash_ctrl_rw_derr	214.430s	17752.691us	10	10	100.00
	flash_ctrl_integrity	476.450s	9456.217us	4	5	80.00
sec_cm_rma_entry_mem_sec_wipe				3	3	100.00
	flash_ctrl_hw_rma	1577.640s	571662.319us	3	3	100.00
sec_cm_ctrl_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2178.350s	3473.675us	5	5	100.00
sec_cm_phy_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2178.350s	3473.675us	5	5	100.00
sec_cm_phy_prog_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2178.350s	3473.675us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2178.350s	3473.675us	5	5	100.00
sec_cm_phy_arbiter_ctrl_redun				4	5	80.00
	flash_ctrl_phy_arb_redun	17.520s	823.844us	4	5	80.00
sec_cm_phy_host_grant_ctrl_consistency				5	5	100.00
	flash_ctrl_phy_host_grant_err	12.880s	23.748us	5	5	100.00
sec_cm_phy_ack_ctrl_consistency				5	5	100.00
	flash_ctrl_phy_ack_consistency	14.810s	171.658us	5	5	100.00
sec_cm_fifo_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2178.350s	3473.675us	5	5	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2178.350s	3473.675us	5	5	100.00
sec_cm_prog_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2178.350s	3473.675us	5	5	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
asymmetric_read_path				1	1	100.00
	flash_ctrl_rd_ooo	31.710s	65.371us	1	1	100.00

unmapped

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				3	3	100.00
	flash_ctrl_basic_rw	318.620s	902.169us	3	3	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:573) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [] vs [*])
	flash_ctrl_integrity	73075752340746149452648892021969139019365180609118222053780627542289090334810	105	UVM_ERROR @ 7212823.1 ns: (flash_ctrl_otf_scoreboard.sv:573) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (1206030274715770716160 [0x416108410820488000] vs 1844908596237907337608 [0x6403400188a1092188]) UVM_INFO @ 7212823.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes
	flash_ctrl_intr_wr_slow_flash	49257308992379532966898900786185607632560606545393529210214312639531958426302	None	Job timed out after 60 minutes
	flash_ctrl_intr_wr	85597852286839279274502385177894567972158517409910249749001857464429887711830	None	Job timed out after 60 minutes
	flash_ctrl_wo	44841061528523963461406650266942271084747779178639063103000396694195819946321	None	Job timed out after 60 minutes
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act () != exp ()
	flash_ctrl_phy_arb_redun	81927876701015422729225884984351495628630144135729016683271766201309345245014	105	UVM_ERROR @ 8642.5 ns: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2a) != exp (0x1f) UVM_INFO @ 8642.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert fatal_err triggered unexpectedly
	flash_ctrl_rw	3369042758836015683942505796738213047871977710297768272599962040799670538343	105	UVM_ERROR @ 569671.3 ns: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly UVM_INFO @ 569671.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_ro	54386837861567997400283676123532006115659711871173115311474773790404684298892	105	UVM_ERROR @ 1052522.9 ns: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly UVM_INFO @ 1052522.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.op_status.err reset value:
	flash_ctrl_rw_evict	94660625191891311156207363356830322897902011583724697896122308940465702124326	105	UVM_ERROR @ 43732.2 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 43732.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict_all_en	97822603950718439088856223732298505770990800605162442960396688078025234422466	105	UVM_ERROR @ 12070.5 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 12070.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict	103750404071889991183021927254436347602586676342327373582585932938766555671550	105	UVM_ERROR @ 46279.5 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 46279.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict_all_en	69729827240061141098531543705318557193529004873727022230397894172175883940419	105	UVM_ERROR @ 9546.3 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 9546.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp f3209cf3_c50d918f:ffffffff_ffffffff mismatch!!
	flash_ctrl_intr_rd	82097537261207941756467603914313128227306731109946500540533926679627570485864	105	UVM_ERROR @ 1391418.7 ns: (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] 2: obs:exp f3209cf3_c50d918f:ffffffff_ffffffff mismatch!! UVM_INFO @ 1391418.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp fef3ea_560174c0:ffffffff_560174c* mismatch!!
	flash_ctrl_intr_rd	109493075697677563089288611113954010061813668627837200387068308752274430212851	105	UVM_ERROR @ 588096.2 ns: (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] 6: obs:exp 67fef3ea_560174c0:ffffffff_560174c0 mismatch!! UVM_INFO @ 588096.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---