Simulation Results: hmac

 
04/01/2026 00:13:51 sha: 05ff44d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.97 %
  • code
  • 99.30 %
  • assert
  • 97.61 %
  • func
  • 100.00 %
  • line
  • 99.95 %
  • branch
  • 99.83 %
  • cond
  • 96.74 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 11.570s 9773.488us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.290s 37.797us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.220s 101.629us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 11.060s 1233.097us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 9.250s 449.661us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 812.090s 207466.750us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.220s 101.629us 20 20 100.00
hmac_csr_aliasing 9.250s 449.661us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 50.580s 1217.076us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 97.990s 7316.773us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 244.890s 26737.744us 30 30 100.00
hmac_test_sha384_vectors 510.260s 90424.119us 75 75 100.00
hmac_test_sha512_vectors 525.850s 93455.539us 75 75 100.00
hmac_test_hmac256_vectors 15.500s 1493.391us 50 50 100.00
hmac_test_hmac384_vectors 16.160s 1473.168us 60 60 100.00
hmac_test_hmac512_vectors 20.200s 439.669us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 41.300s 806.625us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1036.660s 27098.681us 10 10 100.00
error 10 10 100.00
hmac_error 90.800s 45435.612us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 109.530s 11044.068us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 11.570s 9773.488us 10 10 100.00
hmac_long_msg 50.580s 1217.076us 10 10 100.00
hmac_back_pressure 97.990s 7316.773us 25 25 100.00
hmac_datapath_stress 1036.660s 27098.681us 10 10 100.00
hmac_burst_wr 41.300s 806.625us 50 50 100.00
hmac_stress_all 2338.290s 97993.550us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 11.570s 9773.488us 10 10 100.00
hmac_long_msg 50.580s 1217.076us 10 10 100.00
hmac_back_pressure 97.990s 7316.773us 25 25 100.00
hmac_datapath_stress 1036.660s 27098.681us 10 10 100.00
hmac_wipe_secret 109.530s 11044.068us 10 10 100.00
hmac_test_sha256_vectors 244.890s 26737.744us 30 30 100.00
hmac_test_sha384_vectors 510.260s 90424.119us 75 75 100.00
hmac_test_sha512_vectors 525.850s 93455.539us 75 75 100.00
hmac_test_hmac256_vectors 15.500s 1493.391us 50 50 100.00
hmac_test_hmac384_vectors 16.160s 1473.168us 60 60 100.00
hmac_test_hmac512_vectors 20.200s 439.669us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 11.570s 9773.488us 10 10 100.00
hmac_long_msg 50.580s 1217.076us 10 10 100.00
hmac_back_pressure 97.990s 7316.773us 25 25 100.00
hmac_datapath_stress 1036.660s 27098.681us 10 10 100.00
hmac_burst_wr 41.300s 806.625us 50 50 100.00
hmac_error 90.800s 45435.612us 10 10 100.00
hmac_wipe_secret 109.530s 11044.068us 10 10 100.00
hmac_test_sha256_vectors 244.890s 26737.744us 30 30 100.00
hmac_test_sha384_vectors 510.260s 90424.119us 75 75 100.00
hmac_test_sha512_vectors 525.850s 93455.539us 75 75 100.00
hmac_test_hmac256_vectors 15.500s 1493.391us 50 50 100.00
hmac_test_hmac384_vectors 16.160s 1473.168us 60 60 100.00
hmac_test_hmac512_vectors 20.200s 439.669us 75 75 100.00
hmac_stress_all 2338.290s 97993.550us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2338.290s 97993.550us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.920s 42.663us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.970s 27.080us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 4.190s 240.283us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 4.190s 240.283us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.290s 37.797us 5 5 100.00
hmac_csr_rw 1.220s 101.629us 20 20 100.00
hmac_csr_aliasing 9.250s 449.661us 5 5 100.00
hmac_same_csr_outstanding 2.810s 122.071us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.290s 37.797us 5 5 100.00
hmac_csr_rw 1.220s 101.629us 20 20 100.00
hmac_csr_aliasing 9.250s 449.661us 5 5 100.00
hmac_same_csr_outstanding 2.810s 122.071us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_sec_cm 1.170s 78.441us 5 5 100.00
hmac_tl_intg_err 4.360s 228.567us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 4.360s 228.567us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 11.570s 9773.488us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 7.730s 178.372us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 402.340s 6742.562us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.680s 69.375us 1 1 100.00

Error Messages

   Test seed line log context