Simulation Results: keymgr

 
04/01/2026 00:13:51 sha: 05ff44d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.98 %
  • code
  • 98.95 %
  • assert
  • 97.72 %
  • func
  • 91.26 %
  • line
  • 99.13 %
  • branch
  • 99.01 %
  • cond
  • 98.22 %
  • toggle
  • 98.38 %
  • FSM
  • 100.00 %
Validation stages
V1
99.44%
V2
98.93%
V2S
99.81%
V3
62.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 49 50 98.00
keymgr_smoke 24.780s 1514.422us 49 50 98.00
random 50 50 100.00
keymgr_random 45.190s 5790.754us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 1.530s 96.922us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 1.700s 27.819us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 23.430s 1282.281us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 12.410s 950.846us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 2.230s 894.297us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 1.700s 27.819us 20 20 100.00
keymgr_csr_aliasing 12.410s 950.846us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 88.130s 4575.881us 50 50 100.00
sideload 198 200 99.00
keymgr_sideload 38.960s 5854.196us 50 50 100.00
keymgr_sideload_kmac 34.000s 7262.376us 50 50 100.00
keymgr_sideload_aes 43.760s 6640.114us 49 50 98.00
keymgr_sideload_otbn 41.780s 2569.632us 49 50 98.00
direct_to_disabled_state 49 50 98.00
keymgr_direct_to_disabled 15.470s 989.915us 49 50 98.00
lc_disable 49 50 98.00
keymgr_lc_disable 20.350s 2118.385us 49 50 98.00
kmac_error_response 50 50 100.00
keymgr_kmac_rsp_err 5.190s 588.494us 50 50 100.00
invalid_sw_input 50 50 100.00
keymgr_sw_invalid_input 35.960s 2981.185us 50 50 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 41.470s 1906.441us 50 50 100.00
sync_async_fault_cross 49 50 98.00
keymgr_sync_async_fault_cross 7.920s 510.655us 49 50 98.00
stress_all 46 50 92.00
keymgr_stress_all 537.350s 80876.537us 46 50 92.00
intr_test 50 50 100.00
keymgr_intr_test 1.080s 50.410us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.440s 28.569us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 4.390s 127.064us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 4.390s 127.064us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 1.530s 96.922us 5 5 100.00
keymgr_csr_rw 1.700s 27.819us 20 20 100.00
keymgr_csr_aliasing 12.410s 950.846us 5 5 100.00
keymgr_same_csr_outstanding 3.340s 1630.450us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 1.530s 96.922us 5 5 100.00
keymgr_csr_rw 1.700s 27.819us 20 20 100.00
keymgr_csr_aliasing 12.410s 950.846us 5 5 100.00
keymgr_same_csr_outstanding 3.340s 1630.450us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 14.270s 2940.847us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_sec_cm 14.270s 2940.847us 5 5 100.00
keymgr_tl_intg_err 6.770s 844.303us 20 20 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 5.780s 646.934us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 5.780s 646.934us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 5.780s 646.934us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 5.780s 646.934us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 12.410s 484.798us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 14.270s 2940.847us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 14.270s 2940.847us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 6.770s 844.303us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 5.780s 646.934us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 88.130s 4575.881us 50 50 100.00
sec_cm_reseed_config_regwen 70 70 100.00
keymgr_random 45.190s 5790.754us 50 50 100.00
keymgr_csr_rw 1.700s 27.819us 20 20 100.00
sec_cm_sw_binding_config_regwen 70 70 100.00
keymgr_random 45.190s 5790.754us 50 50 100.00
keymgr_csr_rw 1.700s 27.819us 20 20 100.00
sec_cm_max_key_ver_config_regwen 70 70 100.00
keymgr_random 45.190s 5790.754us 50 50 100.00
keymgr_csr_rw 1.700s 27.819us 20 20 100.00
sec_cm_lc_ctrl_intersig_mubi 49 50 98.00
keymgr_lc_disable 20.350s 2118.385us 49 50 98.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 41.470s 1906.441us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 41.470s 1906.441us 50 50 100.00
sec_cm_hw_key_sw_noaccess 50 50 100.00
keymgr_random 45.190s 5790.754us 50 50 100.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 14.580s 1462.401us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 14.270s 2940.847us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 14.270s 2940.847us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 14.270s 2940.847us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 36.580s 4500.804us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 49 50 98.00
keymgr_lc_disable 20.350s 2118.385us 49 50 98.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 14.270s 2940.847us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 14.270s 2940.847us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 14.270s 2940.847us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 36.580s 4500.804us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 36.580s 4500.804us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 14.270s 2940.847us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 36.580s 4500.804us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 14.270s 2940.847us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 36.580s 4500.804us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 31 50 62.00
keymgr_stress_all_with_rand_reset 20.030s 2522.345us 31 50 62.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_stress_all 80383109088590751850082161564921474355103152431625990724425650574883816851302 2849
UVM_ERROR @ 3667752062 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 3667752062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all 79773993555493222869158250325998093169253590362933844993814912212824082847546 1149
UVM_ERROR @ 163401262 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 163401262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_sideload_otbn 75285502685572589445739755712468791586636546683742737221114981346224032459633 110
UVM_ERROR @ 27446746 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 27446746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_smoke 52001032132185527820660279497864283565831569326595836552610192300433881856481 112
UVM_ERROR @ 18690515 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 18690515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_sideload_aes 7894436441514217058404696586970327978656777760486302021320821857124692709271 98
UVM_ERROR @ 4738491 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 4738491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_direct_to_disabled 56794265409611914604484593517033959307604592136072616135308649489152613091496 156
UVM_ERROR @ 19403297 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 19403297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 73529534481497693838001313140492376511476892726527193141035712757102106190538 125
UVM_ERROR @ 205933321 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 205933321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 74181685226455912133470876756916477690450417313336224031229311287673259756072 99
UVM_ERROR @ 116846721 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10009 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 116846721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 68009866365146100675502422077009126357060345181666584984618276847960062856365 572
UVM_ERROR @ 1081234661 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1081234661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 6809205044317512770841762300215991501737257229137486568229519120083808893015 172
UVM_ERROR @ 577968264 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 577968264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 106230046347043179583549461736672133005834935604632714092057363676967752120253 129
UVM_ERROR @ 542610330 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 542610330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 80835308522431372335630237520722683710709143235906274676990345509283283443678 528
UVM_ERROR @ 189632216 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 189632216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 60612104687177451929512757867631308102135778405605571599039784566287475067541 180
UVM_ERROR @ 138613147 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 138613147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 21274857535508846884526128588451837463752288304382618350564501643250250619153 94
UVM_ERROR @ 110427870 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 110427870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 94278589565737993482521859247882746711186404941466178862195910195612882646661 934
UVM_ERROR @ 899085437 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10011 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 899085437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 472146258265532639571223303449866782829997348953228705404120508095952080563 135
UVM_ERROR @ 258843597 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 258843597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 6172368522016217691879770783417110641065269993816260938569612928496334236639 159
UVM_ERROR @ 480655497 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 480655497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 106460867410707011185238593011852812797653143956504863715741577361741094612979 387
UVM_ERROR @ 1491313070 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1491313070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 52317440099926996580181825124444430172447033725262932505622606428705700195916 114
UVM_ERROR @ 217696723 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 217696723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 23420823478231609134798367562433530717558160584350607772042397618792608524636 97
UVM_ERROR @ 111394699 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 111394699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 5871761754605356776658298303355711697225966366580554211597017948325122115635 119
UVM_ERROR @ 211454871 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 211454871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 42727005081737504002091210666880061003541453589032980349750738484353993740346 357
UVM_ERROR @ 285131181 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 285131181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 15960150357590917219367547715250221385274617135184481664555966570808284486080 236
UVM_ERROR @ 112720655 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 112720655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 81280849967760682679510258256900001208864431091319184655609540524508955944041 981
UVM_ERROR @ 1110812342 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1110812342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 65104700962038492690591761685241225059950912317008172701532356841303614990494 171
UVM_ERROR @ 404926371 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 404926371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert recov_operation_err is not received!
keymgr_sync_async_fault_cross 99187567411368398090509068331135127265036912712067933879266679841621580665211 114
UVM_ERROR @ 342865097 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
UVM_INFO @ 342865097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_*
keymgr_stress_all 73110832675670333687195572298518369319859394694607959683143339348903382375480 4036
UVM_ERROR @ 2554430553 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_0
UVM_INFO @ 2554430553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StCreatorRootKey for Attestation Aes
keymgr_stress_all 39319469906570002836909276789833722183355330573399931677122298281652808454994 1741
UVM_ERROR @ 2372199857 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (4858579688108199004011464698300956038159953985583205775032085631650324924884840808591950396349513215423452261766797690100315672799599940527880192293254387 [0x5cc43e29a03616689515421897329a68ab037b2d26dd3a23d4d1b55aba3b0ea5a8ef6cd620c31e1af6cb9caf13738e8ad8fe8ebdc812ba01b1f4c432bc2ab4f3] vs 4858579688108199004011464698300956038159953985583205775032085631650324924884840808591950396349513215423452261766797690100315672799599940527880192293254387 [0x5cc43e29a03616689515421897329a68ab037b2d26dd3a23d4d1b55aba3b0ea5a8ef6cd620c31e1af6cb9caf13738e8ad8fe8ebdc812ba01b1f4c432bc2ab4f3]) AES key at state StCreatorRootKey for Attestation Aes
UVM_INFO @ 2372199857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerKey for Attestation Aes
keymgr_lc_disable 78182359198252759063438444206324818290654089758491804110787388204629053770486 280
UVM_ERROR @ 317155148 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (8031047502785211275224743989341848514338197768116845900669354903859803003502281002426527701961552166295906832150076530451064219266834436153845291051969272 [0x9956f146b5cf72c9422fd1b43ec62a301d7e23dd3fc6ec5b2b807b548a0b7108a6d5e43ee2674e289527f533b6eda1095b826ad06c046b4f5cb9ef644114eaf8] vs 8031047502785211275224743989341848514338197768116845900669354903859803003502281002426527701961552166295906832150076530451064219266834436153845291051969272 [0x9956f146b5cf72c9422fd1b43ec62a301d7e23dd3fc6ec5b2b807b548a0b7108a6d5e43ee2674e289527f533b6eda1095b826ad06c046b4f5cb9ef644114eaf8]) AES key at state StOwnerKey for Attestation Aes
UVM_INFO @ 317155148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---