Simulation Results: kmac

 
04/01/2026 00:13:51 sha: 05ff44d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.73 %
  • code
  • 94.49 %
  • assert
  • 97.83 %
  • func
  • 97.86 %
  • line
  • 99.27 %
  • branch
  • 97.15 %
  • cond
  • 94.45 %
  • toggle
  • 99.89 %
  • FSM
  • 81.69 %
Validation stages
V1
100.00%
V2
99.88%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 91.400s 3495.677us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.500s 63.790us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.240s 37.016us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 14.590s 5236.670us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 7.340s 1936.314us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.830s 444.912us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.240s 37.016us 20 20 100.00
kmac_csr_aliasing 7.340s 1936.314us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 0.880s 17.834us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.410s 114.580us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3956.650s 92347.456us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1650.650s 38237.119us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2333.160s 387179.239us 5 5 100.00
kmac_test_vectors_sha3_256 2057.680s 87836.873us 5 5 100.00
kmac_test_vectors_sha3_384 2019.120s 87383.817us 5 5 100.00
kmac_test_vectors_sha3_512 1251.650s 254839.080us 5 5 100.00
kmac_test_vectors_shake_128 3118.290s 295066.983us 5 5 100.00
kmac_test_vectors_shake_256 1935.140s 61726.077us 5 5 100.00
kmac_test_vectors_kmac 3.330s 385.739us 5 5 100.00
kmac_test_vectors_kmac_xof 3.840s 91.393us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 629.640s 45054.530us 50 50 100.00
app 50 50 100.00
kmac_app 400.310s 23479.914us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 317.380s 28902.430us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 432.500s 147721.012us 50 50 100.00
error 50 50 100.00
kmac_error 453.010s 81993.714us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 21.650s 27072.884us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 9.170s 147.254us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 55.480s 1797.524us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 33.510s 1914.688us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 67.030s 24911.495us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 36.510s 1364.554us 50 50 100.00
stress_all 49 50 98.00
kmac_stress_all 3036.480s 444305.485us 49 50 98.00
intr_test 50 50 100.00
kmac_intr_test 0.970s 35.648us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.250s 81.489us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.460s 56.191us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.460s 56.191us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.500s 63.790us 5 5 100.00
kmac_csr_rw 1.240s 37.016us 20 20 100.00
kmac_csr_aliasing 7.340s 1936.314us 5 5 100.00
kmac_same_csr_outstanding 2.340s 90.521us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.500s 63.790us 5 5 100.00
kmac_csr_rw 1.240s 37.016us 20 20 100.00
kmac_csr_aliasing 7.340s 1936.314us 5 5 100.00
kmac_same_csr_outstanding 2.340s 90.521us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.150s 1511.799us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.150s 1511.799us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.150s 1511.799us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.150s 1511.799us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 3.890s 260.487us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 4.010s 295.515us 20 20 100.00
kmac_sec_cm 117.680s 23156.215us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 4.010s 295.515us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 36.510s 1364.554us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 91.400s 3495.677us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 629.640s 45054.530us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.150s 1511.799us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 117.680s 23156.215us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 117.680s 23156.215us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 117.680s 23156.215us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 91.400s 3495.677us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 36.510s 1364.554us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 117.680s 23156.215us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 378.950s 20515.164us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 91.400s 3495.677us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
kmac_stress_all_with_rand_reset 253.720s 3898.529us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 2121316755805211720409016330399763003502286298332077685837824435495352492065 204
UVM_ERROR @ 4810079590 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 4810079590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
kmac_stress_all 103393584198693749794442453333362916633319263638532678574468410813689113015096 158
UVM_ERROR @ 55623794573 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 55623794573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---