Simulation Results: kmac

 
04/01/2026 00:13:51 sha: 05ff44d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.39 %
  • code
  • 92.30 %
  • assert
  • 97.74 %
  • func
  • 96.12 %
  • line
  • 97.59 %
  • branch
  • 95.97 %
  • cond
  • 94.41 %
  • toggle
  • 100.00 %
  • FSM
  • 73.55 %
Validation stages
V1
100.00%
V2
98.10%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 69.430s 7704.727us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.140s 98.587us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.090s 20.007us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 12.830s 2496.264us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 6.680s 539.601us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 1.890s 335.213us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.090s 20.007us 20 20 100.00
kmac_csr_aliasing 6.680s 539.601us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 0.770s 24.837us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.390s 75.024us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3121.930s 536092.089us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 931.620s 120140.872us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2042.190s 227918.598us 5 5 100.00
kmac_test_vectors_sha3_256 1684.950s 247149.721us 5 5 100.00
kmac_test_vectors_sha3_384 1030.820s 13271.636us 5 5 100.00
kmac_test_vectors_sha3_512 823.090s 386290.643us 5 5 100.00
kmac_test_vectors_shake_128 221.950s 191683.669us 5 5 100.00
kmac_test_vectors_shake_256 1835.250s 85035.496us 5 5 100.00
kmac_test_vectors_kmac 3.060s 270.061us 5 5 100.00
kmac_test_vectors_kmac_xof 3.090s 556.116us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 333.020s 13416.321us 50 50 100.00
app 50 50 100.00
kmac_app 299.180s 52143.038us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 313.650s 41590.951us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 343.310s 266627.204us 50 50 100.00
error 49 50 98.00
kmac_error 423.240s 19773.417us 49 50 98.00
key_error 50 50 100.00
kmac_key_error 14.910s 9517.195us 50 50 100.00
sideload_invalid 35 50 70.00
kmac_sideload_invalid 120.940s 10036.430us 35 50 70.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 41.970s 2075.877us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 32.390s 1172.153us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 60.030s 6972.355us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 29.590s 1083.889us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2325.900s 172159.826us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 0.880s 48.459us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.190s 128.456us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.390s 725.649us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.390s 725.649us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.140s 98.587us 5 5 100.00
kmac_csr_rw 1.090s 20.007us 20 20 100.00
kmac_csr_aliasing 6.680s 539.601us 5 5 100.00
kmac_same_csr_outstanding 2.090s 129.224us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.140s 98.587us 5 5 100.00
kmac_csr_rw 1.090s 20.007us 20 20 100.00
kmac_csr_aliasing 6.680s 539.601us 5 5 100.00
kmac_same_csr_outstanding 2.090s 129.224us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 1.710s 100.738us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 1.710s 100.738us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 1.710s 100.738us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 1.710s 100.738us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 3.750s 388.496us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 3.650s 225.800us 20 20 100.00
kmac_sec_cm 55.240s 10544.242us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 3.650s 225.800us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 29.590s 1083.889us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 69.430s 7704.727us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 333.020s 13416.321us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 1.710s 100.738us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 55.240s 10544.242us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 55.240s 10544.242us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 55.240s 10544.242us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 69.430s 7704.727us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 29.590s 1083.889us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 55.240s 10544.242us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 259.470s 50366.102us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 69.430s 7704.727us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
kmac_stress_all_with_rand_reset 207.510s 21215.308us 8 10 80.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
kmac_sideload_invalid 23147731737219739016868237110317261319097914421068150736805121528855263641281 75
UVM_FATAL @ 10035868178 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x97d46000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10035868178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 91630737858246341808814101840160602779418359727811340705105996871905086536076 75
UVM_FATAL @ 10039196789 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7105000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10039196789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 13994707813635825194675444046204354095120709094517549403654970883919463117536 75
UVM_FATAL @ 10008571022 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4f039000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10008571022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 2869790221514281101181501485128615316836761514267000529076346277085986904832 75
UVM_FATAL @ 10009383018 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1f981000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10009383018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 50608346617582156161828612779121943611977885205643374516967114257686540302833 212
UVM_ERROR @ 16355726526 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 16355726526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12)
kmac_sideload_invalid 17944697125498766479914162766272740696510472933566118111142663056260601197921 86
UVM_FATAL @ 10374213746 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9725f000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10374213746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 73556698401565195563316458026791023268496036105122503653751508677893638057808 85
UVM_FATAL @ 10066434355 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x12bf7000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
UVM_INFO @ 10066434355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 70554687945422020431020687472204902653547030736602048739688651431935223987097 191
UVM_ERROR @ 1437473956 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 1437473956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
kmac_sideload_invalid 4564050402370921382209942598875543750611643819389991397184338173892712319830 76
UVM_FATAL @ 10257860842 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x98fcf000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10257860842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 87102404021947291102134427803233637119188262593789103681256879545066438899351 76
UVM_FATAL @ 10082790736 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x17231000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10082790736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8)
kmac_sideload_invalid 109689088960680527503163219001773486667541817516545151928443566195459859893999 82
UVM_FATAL @ 10182465213 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x90410000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10182465213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 48553328322737524554535924963117298196972121600786432907708626177693901345930 82
UVM_FATAL @ 10386995893 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb7740000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10386995893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 64932599498206067629129667692623621012840930015647583435077619107645211669151 81
UVM_FATAL @ 10116206831 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xecbbf000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10116206831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11)
kmac_sideload_invalid 12023732934124548736121147293960033817375838795403075831589131382982716941185 88
UVM_FATAL @ 10290958861 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd1a2c000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10290958861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6)
kmac_sideload_invalid 18094243384160168941570558890172253223336650992519924546949831235671366555534 79
UVM_FATAL @ 10037759781 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xfc29e000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10037759781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
kmac_error 68549852479444034435855555890077058086158055701431616410964385780962898437832 171
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4)
kmac_sideload_invalid 105074762228039295152998307818695244949740403763516050668574830773259313781590 78
UVM_FATAL @ 10092444041 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdb91e000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10092444041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)
kmac_sideload_invalid 1986578050633888066715833796809330542866542412298065548504552567496546336579 81
UVM_FATAL @ 10036430216 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x68a48000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10036430216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---