Simulation Results: otbn

 
04/01/2026 00:13:51 sha: 05ff44d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.75 %
  • code
  • 97.08 %
  • assert
  • 96.16 %
  • func
  • 100.00 %
  • block
  • 99.58 %
  • line
  • 99.68 %
  • branch
  • 95.02 %
  • toggle
  • 93.60 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
97.50%
V3
30.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 21.000s 97.258us 1 1 100.00
single_binary 100 100 100.00
otbn_single 248.000s 861.646us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 13.000s 48.677us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 8.000s 14.560us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 13.000s 135.425us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 9.000s 42.513us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 13.000s 144.666us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 8.000s 14.560us 20 20 100.00
otbn_csr_aliasing 9.000s 42.513us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 44.000s 865.984us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 20.000s 727.012us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 53.000s 221.056us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 82.000s 218.949us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 56.000s 308.546us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 126.000s 531.513us 10 10 100.00
lc_escalation 60 60 100.00
otbn_escalate 33.000s 127.531us 60 60 100.00
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 9.000s 59.774us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 15.000s 1278.298us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 9.000s 29.305us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 10.000s 18.573us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 11.000s 147.622us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 11.000s 147.622us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 13.000s 48.677us 5 5 100.00
otbn_csr_rw 8.000s 14.560us 20 20 100.00
otbn_csr_aliasing 9.000s 42.513us 5 5 100.00
otbn_same_csr_outstanding 9.000s 43.020us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 13.000s 48.677us 5 5 100.00
otbn_csr_rw 8.000s 14.560us 20 20 100.00
otbn_csr_aliasing 9.000s 42.513us 5 5 100.00
otbn_same_csr_outstanding 9.000s 43.020us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 9.000s 18.017us 10 10 100.00
otbn_dmem_err 11.000s 39.704us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 7.000s 165.035us 5 5 100.00
otbn_controller_ispr_rdata_err 10.000s 29.236us 5 5 100.00
otbn_mac_bignum_acc_err 19.000s 114.971us 5 5 100.00
otbn_urnd_err 8.000s 24.589us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 9.000s 38.690us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 6.000s 51.828us 2 2 100.00
otbn_non_sec_partial_wipe 10 10 100.00
otbn_partial_wipe 6.000s 45.535us 10 10 100.00
tl_intg_err 23 25 92.00
otbn_tl_intg_err 26.000s 716.969us 20 20 100.00
otbn_sec_cm 481.000s 2064.639us 3 5 60.00
passthru_mem_tl_intg_err 19 20 95.00
otbn_passthru_mem_tl_intg_err 63.000s 366.454us 19 20 95.00
prim_fsm_check 3 5 60.00
otbn_sec_cm 481.000s 2064.639us 3 5 60.00
prim_count_check 3 5 60.00
otbn_sec_cm 481.000s 2064.639us 3 5 60.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 21.000s 97.258us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 11.000s 39.704us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 9.000s 18.017us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 26.000s 716.969us 20 20 100.00
sec_cm_controller_fsm_global_esc 60 60 100.00
otbn_escalate 33.000s 127.531us 60 60 100.00
sec_cm_controller_fsm_local_esc 38 40 95.00
otbn_imem_err 9.000s 18.017us 10 10 100.00
otbn_dmem_err 11.000s 39.704us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 59.774us 5 5 100.00
otbn_illegal_mem_acc 9.000s 38.690us 5 5 100.00
otbn_sec_cm 481.000s 2064.639us 3 5 60.00
sec_cm_controller_fsm_sparse 3 5 60.00
otbn_sec_cm 481.000s 2064.639us 3 5 60.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 248.000s 861.646us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 38 40 95.00
otbn_imem_err 9.000s 18.017us 10 10 100.00
otbn_dmem_err 11.000s 39.704us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 59.774us 5 5 100.00
otbn_illegal_mem_acc 9.000s 38.690us 5 5 100.00
otbn_sec_cm 481.000s 2064.639us 3 5 60.00
sec_cm_scramble_ctrl_fsm_sparse 3 5 60.00
otbn_sec_cm 481.000s 2064.639us 3 5 60.00
sec_cm_start_stop_ctrl_fsm_global_esc 60 60 100.00
otbn_escalate 33.000s 127.531us 60 60 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 38 40 95.00
otbn_imem_err 9.000s 18.017us 10 10 100.00
otbn_dmem_err 11.000s 39.704us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 59.774us 5 5 100.00
otbn_illegal_mem_acc 9.000s 38.690us 5 5 100.00
otbn_sec_cm 481.000s 2064.639us 3 5 60.00
sec_cm_start_stop_ctrl_fsm_sparse 3 5 60.00
otbn_sec_cm 481.000s 2064.639us 3 5 60.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 248.000s 861.646us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 13.000s 68.528us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 10.000s 29.861us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 63.000s 590.563us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 63.000s 590.563us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 9 10 90.00
otbn_rf_base_intg_err 15.000s 2077.930us 9 10 90.00
sec_cm_rf_base_data_reg_sw_glitch_detect 3 5 60.00
otbn_sec_cm 481.000s 2064.639us 3 5 60.00
sec_cm_stack_wr_ptr_ctr_redun 3 5 60.00
otbn_sec_cm 481.000s 2064.639us 3 5 60.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 14.000s 59.399us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 3 5 60.00
otbn_sec_cm 481.000s 2064.639us 3 5 60.00
sec_cm_loop_stack_ctr_redun 3 5 60.00
otbn_sec_cm 481.000s 2064.639us 3 5 60.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 8.000s 27.285us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 8.000s 27.285us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 4 7 57.14
otbn_sec_wipe_err 14.000s 23.061us 4 7 57.14
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 248.000s 861.646us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 248.000s 861.646us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 248.000s 861.646us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 56.000s 308.546us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 248.000s 861.646us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 248.000s 861.646us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 18.000s 204.466us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 248.000s 861.646us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 3 5 60.00
otbn_sec_cm 481.000s 2064.639us 3 5 60.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
otbn_stress_all_with_rand_reset 355.000s 5157.947us 3 10 30.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 34881733177025294517509277682369227109928421138351898270305781919638882145384 88
UVM_FATAL @ 30275813 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 30275813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 106312468127162717737846623749981042611142915803921849292865144132725403230193 233
UVM_FATAL @ 318530506 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 318530506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 71055500545610998178352870678226620287361201122137471949491624529352718277127 347
UVM_FATAL @ 762026848 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 762026848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed
otbn_sec_cm 19391715329641133397802382407992664947712325056382407551771265212005760664767 91
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 52498785 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 52498785 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 52498785 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 52498785 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 52498785 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
otbn_sec_cm 39080005015315844343020814235306234362643861640560311192706913479365052912188 119
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 157031231 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 157031231 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 157031231 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 157031231 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 157031231 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_sec_wipe_err 688316940787502041951102176964746825382747338272777438497142026592676966650 110
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 27808495 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 27808495 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 27808495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_wipe_err 20111854254491214598592340368236037234194061745051565379522288313623958021477 119
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 23061453 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 23061453 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 23061453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_wipe_err 58816333173403394054271603786806254959035743189171754346308014772734356364069 110
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 27023708 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 27023708 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 27023708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 84601832702640018449160970625155503897611855981460924090318268901781761164097 191
UVM_ERROR @ 2580946965 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2580946965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 50400395620817298821233192042459738518610104175563876011060961215672716562648 481
UVM_ERROR @ 5798778732 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5798778732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 82027665768374467771490315677047271909022594915270646333038222963168004150990 251
UVM_ERROR @ 5157946881 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5157946881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:372) [csr_utils_pkg::csr_rd_sub.isolation_fork] Timeout waiting to csr_rd otbn_reg_block.err_bits (addr=*)
otbn_stress_all_with_rand_reset 97484862247990095616827415061557337499222705755368269315268338869845966356935 489
UVM_FATAL @ 12111121233 ps: (csr_utils_pkg.sv:372) [csr_utils_pkg::csr_rd_sub.isolation_fork] Timeout waiting to csr_rd otbn_reg_block.err_bits (addr=0x6c46001c)
UVM_INFO @ 12111121233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:372) [csr_utils_pkg::csr_rd_sub.isolation_fork] Timeout waiting to csr_rd otbn_reg_block.status (addr=*)
otbn_rf_base_intg_err 72408500740339376893547918810977911747460322582019577303582999785156354261618 114
UVM_FATAL @ 2077929559 ps: (csr_utils_pkg.sv:372) [csr_utils_pkg::csr_rd_sub.isolation_fork] Timeout waiting to csr_rd otbn_reg_block.status (addr=0x4640018)
UVM_INFO @ 2077929559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 56084924972376381938987004302760293450511847447493316169052886742077551599268 222
UVM_FATAL @ 2453765834 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 2453765834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---