| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
89.31% |
| V3 |
|
95.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 7.080s | 137.028us | 2 | 2 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 8.130s | 129.242us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| rom_ctrl_csr_rw | 5.700s | 536.097us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| rom_ctrl_csr_bit_bash | 7.280s | 165.695us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| rom_ctrl_csr_aliasing | 5.330s | 126.136us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| rom_ctrl_csr_mem_rw_with_rand_reset | 6.170s | 175.179us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| rom_ctrl_csr_rw | 5.700s | 536.097us | 20 | 20 | 100.00 | |
| rom_ctrl_csr_aliasing | 5.330s | 126.136us | 5 | 5 | 100.00 | |
| mem_walk | 5 | 5 | 100.00 | |||
| rom_ctrl_mem_walk | 7.230s | 1865.654us | 5 | 5 | 100.00 | |
| mem_partial_access | 5 | 5 | 100.00 | |||
| rom_ctrl_mem_partial_access | 5.470s | 128.675us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_throughput_chk | 2 | 2 | 100.00 | |||
| rom_ctrl_max_throughput_chk | 4.980s | 646.560us | 2 | 2 | 100.00 | |
| stress_all | 20 | 20 | 100.00 | |||
| rom_ctrl_stress_all | 34.640s | 7194.803us | 20 | 20 | 100.00 | |
| kmac_err_chk | 2 | 2 | 100.00 | |||
| rom_ctrl_kmac_err_chk | 10.100s | 1236.412us | 2 | 2 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| rom_ctrl_alert_test | 6.960s | 165.114us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| rom_ctrl_tl_errors | 11.120s | 700.998us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| rom_ctrl_tl_errors | 11.120s | 700.998us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 8.130s | 129.242us | 5 | 5 | 100.00 | |
| rom_ctrl_csr_rw | 5.700s | 536.097us | 20 | 20 | 100.00 | |
| rom_ctrl_csr_aliasing | 5.330s | 126.136us | 5 | 5 | 100.00 | |
| rom_ctrl_same_csr_outstanding | 7.150s | 323.683us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 8.130s | 129.242us | 5 | 5 | 100.00 | |
| rom_ctrl_csr_rw | 5.700s | 536.097us | 20 | 20 | 100.00 | |
| rom_ctrl_csr_aliasing | 5.330s | 126.136us | 5 | 5 | 100.00 | |
| rom_ctrl_same_csr_outstanding | 7.150s | 323.683us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| corrupt_sig_fatal_chk | 19 | 20 | 95.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 125.390s | 7311.993us | 19 | 20 | 95.00 | |
| passthru_mem_tl_intg_err | 20 | 20 | 100.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 29.180s | 3331.996us | 20 | 20 | 100.00 | |
| tl_intg_err | 21 | 25 | 84.00 | |||
| rom_ctrl_sec_cm | 233.660s | 1807.605us | 1 | 5 | 20.00 | |
| rom_ctrl_tl_intg_err | 63.020s | 1139.586us | 20 | 20 | 100.00 | |
| prim_fsm_check | 1 | 5 | 20.00 | |||
| rom_ctrl_sec_cm | 233.660s | 1807.605us | 1 | 5 | 20.00 | |
| prim_count_check | 1 | 5 | 20.00 | |||
| rom_ctrl_sec_cm | 233.660s | 1807.605us | 1 | 5 | 20.00 | |
| sec_cm_checker_ctr_consistency | 19 | 20 | 95.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 125.390s | 7311.993us | 19 | 20 | 95.00 | |
| sec_cm_checker_ctrl_flow_consistency | 19 | 20 | 95.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 125.390s | 7311.993us | 19 | 20 | 95.00 | |
| sec_cm_checker_fsm_local_esc | 19 | 20 | 95.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 125.390s | 7311.993us | 19 | 20 | 95.00 | |
| sec_cm_compare_ctrl_flow_consistency | 19 | 20 | 95.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 125.390s | 7311.993us | 19 | 20 | 95.00 | |
| sec_cm_compare_ctr_consistency | 19 | 20 | 95.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 125.390s | 7311.993us | 19 | 20 | 95.00 | |
| sec_cm_compare_ctr_redun | 1 | 5 | 20.00 | |||
| rom_ctrl_sec_cm | 233.660s | 1807.605us | 1 | 5 | 20.00 | |
| sec_cm_fsm_sparse | 1 | 5 | 20.00 | |||
| rom_ctrl_sec_cm | 233.660s | 1807.605us | 1 | 5 | 20.00 | |
| sec_cm_mem_scramble | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 7.080s | 137.028us | 2 | 2 | 100.00 | |
| sec_cm_mem_digest | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 7.080s | 137.028us | 2 | 2 | 100.00 | |
| sec_cm_intersig_mubi | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 7.080s | 137.028us | 2 | 2 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| rom_ctrl_tl_intg_err | 63.020s | 1139.586us | 20 | 20 | 100.00 | |
| sec_cm_bus_local_esc | 21 | 22 | 95.45 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 125.390s | 7311.993us | 19 | 20 | 95.00 | |
| rom_ctrl_kmac_err_chk | 10.100s | 1236.412us | 2 | 2 | 100.00 | |
| sec_cm_mux_mubi | 19 | 20 | 95.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 125.390s | 7311.993us | 19 | 20 | 95.00 | |
| sec_cm_mux_consistency | 19 | 20 | 95.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 125.390s | 7311.993us | 19 | 20 | 95.00 | |
| sec_cm_ctrl_redun | 19 | 20 | 95.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 125.390s | 7311.993us | 19 | 20 | 95.00 | |
| sec_cm_ctrl_mem_integrity | 20 | 20 | 100.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 29.180s | 3331.996us | 20 | 20 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 1 | 5 | 20.00 | |||
| rom_ctrl_sec_cm | 233.660s | 1807.605us | 1 | 5 | 20.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 19 | 20 | 95.00 | |||
| rom_ctrl_stress_all_with_rand_reset | 490.400s | 20451.400us | 19 | 20 | 95.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' | ||||
| rom_ctrl_sec_cm | 62512721810542727645713697446925735207139666374789238667423967089500732467329 | 371 |
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 92070786ps failed at 92070786ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 99591681ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 99591681ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
|
|
| Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' | ||||
| rom_ctrl_sec_cm | 19554676927679983224625970180643059954040636054959588079840486671557179867721 | 675 |
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 285999938ps failed at 285999938ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 285999938ps failed at 285999938ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
|
|
| rom_ctrl_sec_cm | 63057054222748755997855205401032413764352810891882805694212073423927089321469 | 166 |
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 30908697ps failed at 30908697ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 30908697ps failed at 30908697ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
|
|
| Offending '(curr_fwd | pend_req[d2h.d_source].pend)' | ||||
| rom_ctrl_sec_cm | 79609675937955667760610846456832098276531152318065903506031421953286413492555 | 106 |
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 11484107ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 11484107ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Starting assertion attempts at time 11484107ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))
|
|
| UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire | ||||
| rom_ctrl_stress_all_with_rand_reset | 64260801246464378134352573306500758350494031355171079450810924758187022434678 | 145 |
UVM_ERROR @ 5137802159 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire
UVM_INFO @ 5137802159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) | ||||
| rom_ctrl_corrupt_sig_fatal_chk | 64784770976383522677836651497834953221928320702832856830523989110598246686445 | 97 |
UVM_ERROR @ 2005006288 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 2005006288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|