Simulation Results: rom_ctrl

 
04/01/2026 00:13:51 sha: 05ff44d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.54 %
  • code
  • 99.55 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.46 %
  • branch
  • 99.64 %
  • cond
  • 98.66 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
94.34%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 8.080s 394.995us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 15.490s 1041.397us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 13.580s 4141.924us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 8.740s 295.697us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 10.470s 298.835us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 11.650s 315.306us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 13.580s 4141.924us 20 20 100.00
rom_ctrl_csr_aliasing 10.470s 298.835us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 9.430s 212.390us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 10.040s 4146.888us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 11.050s 222.386us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 50.870s 8304.558us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 16.060s 1700.317us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 12.300s 1058.850us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 14.340s 544.206us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 14.340s 544.206us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 15.490s 1041.397us 5 5 100.00
rom_ctrl_csr_rw 13.580s 4141.924us 20 20 100.00
rom_ctrl_csr_aliasing 10.470s 298.835us 5 5 100.00
rom_ctrl_same_csr_outstanding 14.980s 1057.644us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 15.490s 1041.397us 5 5 100.00
rom_ctrl_csr_rw 13.580s 4141.924us 20 20 100.00
rom_ctrl_csr_aliasing 10.470s 298.835us 5 5 100.00
rom_ctrl_same_csr_outstanding 14.980s 1057.644us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 399.730s 119936.232us 20 20 100.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 60.370s 4021.538us 20 20 100.00
tl_intg_err 22 25 88.00
rom_ctrl_tl_intg_err 127.880s 358.764us 20 20 100.00
rom_ctrl_sec_cm 616.090s 16623.437us 2 5 40.00
prim_fsm_check 2 5 40.00
rom_ctrl_sec_cm 616.090s 16623.437us 2 5 40.00
prim_count_check 2 5 40.00
rom_ctrl_sec_cm 616.090s 16623.437us 2 5 40.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 399.730s 119936.232us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 399.730s 119936.232us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 399.730s 119936.232us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 399.730s 119936.232us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 399.730s 119936.232us 20 20 100.00
sec_cm_compare_ctr_redun 2 5 40.00
rom_ctrl_sec_cm 616.090s 16623.437us 2 5 40.00
sec_cm_fsm_sparse 2 5 40.00
rom_ctrl_sec_cm 616.090s 16623.437us 2 5 40.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 8.080s 394.995us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 8.080s 394.995us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 8.080s 394.995us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 127.880s 358.764us 20 20 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 399.730s 119936.232us 20 20 100.00
rom_ctrl_kmac_err_chk 16.060s 1700.317us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 399.730s 119936.232us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 399.730s 119936.232us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 399.730s 119936.232us 20 20 100.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 60.370s 4021.538us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 2 5 40.00
rom_ctrl_sec_cm 616.090s 16623.437us 2 5 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 293.080s 11178.146us 20 20 100.00

Error Messages

   Test seed line log context
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
rom_ctrl_sec_cm 12102393539869583321218737379516256277375685664652606054974272635103495826598 162
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 34374675ps failed at 34374675ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 56812176ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 56812176ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
rom_ctrl_sec_cm 95993705172335784366053221881742460558159139423340642211602324989142779052286 165
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 17725401ps failed at 17725401ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 17725401ps failed at 17725401ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 113149860143335474384076213007413042344641562863959363781165844706777699335308 242
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 12822566ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 12822566ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
Starting assertion attempts at time 12822566ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))