Simulation Results: rstmgr

 
04/01/2026 00:13:51 sha: 05ff44d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.86 %
  • code
  • 99.68 %
  • assert
  • 98.13 %
  • func
  • 98.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 99.38 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
rstmgr_smoke 2.040s 258.487us 50 50 100.00
csr_hw_reset 5 5 100.00
rstmgr_csr_hw_reset 1.020s 142.199us 5 5 100.00
csr_rw 20 20 100.00
rstmgr_csr_rw 0.990s 70.447us 20 20 100.00
csr_bit_bash 5 5 100.00
rstmgr_csr_bit_bash 6.510s 1570.544us 5 5 100.00
csr_aliasing 5 5 100.00
rstmgr_csr_aliasing 2.660s 430.734us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.530s 164.572us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rstmgr_csr_rw 0.990s 70.447us 20 20 100.00
rstmgr_csr_aliasing 2.660s 430.734us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 50 50 100.00
rstmgr_por_stretcher 1.410s 216.371us 50 50 100.00
sw_rst 50 50 100.00
rstmgr_sw_rst 2.830s 495.786us 50 50 100.00
sw_rst_reset_race 50 50 100.00
rstmgr_sw_rst_reset_race 1.910s 265.950us 50 50 100.00
reset_info 50 50 100.00
rstmgr_reset 8.920s 2155.499us 50 50 100.00
cpu_info 50 50 100.00
rstmgr_reset 8.920s 2155.499us 50 50 100.00
alert_info 50 50 100.00
rstmgr_reset 8.920s 2155.499us 50 50 100.00
reset_info_capture 50 50 100.00
rstmgr_reset 8.920s 2155.499us 50 50 100.00
stress_all 50 50 100.00
rstmgr_stress_all 38.180s 15093.610us 50 50 100.00
alert_test 50 50 100.00
rstmgr_alert_test 1.400s 169.243us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rstmgr_tl_errors 3.610s 567.403us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rstmgr_tl_errors 3.610s 567.403us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rstmgr_csr_hw_reset 1.020s 142.199us 5 5 100.00
rstmgr_csr_rw 0.990s 70.447us 20 20 100.00
rstmgr_csr_aliasing 2.660s 430.734us 5 5 100.00
rstmgr_same_csr_outstanding 1.750s 239.827us 20 20 100.00
tl_d_partial_access 50 50 100.00
rstmgr_csr_hw_reset 1.020s 142.199us 5 5 100.00
rstmgr_csr_rw 0.990s 70.447us 20 20 100.00
rstmgr_csr_aliasing 2.660s 430.734us 5 5 100.00
rstmgr_same_csr_outstanding 1.750s 239.827us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rstmgr_tl_intg_err 3.400s 967.831us 20 20 100.00
rstmgr_sec_cm 30.720s 16839.252us 5 5 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 30.720s 16839.252us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 30.720s 16839.252us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
rstmgr_tl_intg_err 3.400s 967.831us 20 20 100.00
sec_cm_scan_intersig_mubi 50 50 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.670s 183.986us 50 50 100.00
sec_cm_leaf_rst_bkgn_chk 50 50 100.00
rstmgr_leaf_rst_cnsty 10.100s 1961.755us 50 50 100.00
sec_cm_leaf_rst_shadow 50 50 100.00
rstmgr_leaf_rst_shadow_attack 1.820s 302.746us 50 50 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 30.720s 16839.252us 5 5 100.00
sec_cm_sw_rst_config_regwen 20 20 100.00
rstmgr_csr_rw 0.990s 70.447us 20 20 100.00
sec_cm_dump_ctrl_config_regwen 20 20 100.00
rstmgr_csr_rw 0.990s 70.447us 20 20 100.00

Error Messages

   Test seed line log context