Simulation Results: spi_device

 
04/01/2026 00:13:51 sha: 05ff44d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.98 %
  • code
  • 94.28 %
  • assert
  • 94.41 %
  • func
  • 99.26 %
  • line
  • 99.17 %
  • branch
  • 98.49 %
  • cond
  • 96.65 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
98.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_device_flash_and_tpm 395.140s 103155.428us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_device_csr_hw_reset 1.590s 81.546us 5 5 100.00
csr_rw 20 20 100.00
spi_device_csr_rw 2.910s 144.728us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_device_csr_bit_bash 34.850s 2701.970us 5 5 100.00
csr_aliasing 5 5 100.00
spi_device_csr_aliasing 19.450s 14027.283us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_device_csr_mem_rw_with_rand_reset 3.880s 287.790us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_device_csr_rw 2.910s 144.728us 20 20 100.00
spi_device_csr_aliasing 19.450s 14027.283us 5 5 100.00
mem_walk 5 5 100.00
spi_device_mem_walk 0.920s 17.846us 5 5 100.00
mem_partial_access 5 5 100.00
spi_device_mem_partial_access 2.590s 24.682us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 50 50 100.00
spi_device_csb_read 1.230s 117.078us 50 50 100.00
mem_parity 20 20 100.00
spi_device_mem_parity 1.460s 28.737us 20 20 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 1.100s 45.992us 1 1 100.00
tpm_read 50 50 100.00
spi_device_tpm_rw 8.880s 390.668us 50 50 100.00
tpm_write 50 50 100.00
spi_device_tpm_rw 8.880s 390.668us 50 50 100.00
tpm_hw_reg 100 100 100.00
spi_device_tpm_read_hw_reg 20.480s 5102.788us 50 50 100.00
spi_device_tpm_sts_read 1.440s 141.204us 50 50 100.00
tpm_fully_random_case 50 50 100.00
spi_device_tpm_all 43.940s 15085.497us 50 50 100.00
pass_cmd_filtering 100 100 100.00
spi_device_pass_cmd_filtering 34.090s 11562.138us 50 50 100.00
spi_device_flash_all 256.320s 101037.887us 50 50 100.00
pass_addr_translation 100 100 100.00
spi_device_pass_addr_payload_swap 25.190s 12772.827us 50 50 100.00
spi_device_flash_all 256.320s 101037.887us 50 50 100.00
pass_payload_translation 100 100 100.00
spi_device_pass_addr_payload_swap 25.190s 12772.827us 50 50 100.00
spi_device_flash_all 256.320s 101037.887us 50 50 100.00
cmd_info_slots 50 50 100.00
spi_device_flash_all 256.320s 101037.887us 50 50 100.00
cmd_read_status 100 100 100.00
spi_device_intercept 31.980s 9333.193us 50 50 100.00
spi_device_flash_all 256.320s 101037.887us 50 50 100.00
cmd_read_jedec 100 100 100.00
spi_device_intercept 31.980s 9333.193us 50 50 100.00
spi_device_flash_all 256.320s 101037.887us 50 50 100.00
cmd_read_sfdp 100 100 100.00
spi_device_intercept 31.980s 9333.193us 50 50 100.00
spi_device_flash_all 256.320s 101037.887us 50 50 100.00
cmd_fast_read 100 100 100.00
spi_device_intercept 31.980s 9333.193us 50 50 100.00
spi_device_flash_all 256.320s 101037.887us 50 50 100.00
cmd_read_pipeline 100 100 100.00
spi_device_intercept 31.980s 9333.193us 50 50 100.00
spi_device_flash_all 256.320s 101037.887us 50 50 100.00
flash_cmd_upload 50 50 100.00
spi_device_upload 32.070s 12149.175us 50 50 100.00
mailbox_command 50 50 100.00
spi_device_mailbox 79.360s 73680.291us 50 50 100.00
mailbox_cross_outside_command 50 50 100.00
spi_device_mailbox 79.360s 73680.291us 50 50 100.00
mailbox_cross_inside_command 50 50 100.00
spi_device_mailbox 79.360s 73680.291us 50 50 100.00
cmd_read_buffer 100 100 100.00
spi_device_flash_mode 49.820s 3756.649us 50 50 100.00
spi_device_read_buffer_direct 17.050s 7118.934us 50 50 100.00
cmd_dummy_cycle 100 100 100.00
spi_device_mailbox 79.360s 73680.291us 50 50 100.00
spi_device_flash_all 256.320s 101037.887us 50 50 100.00
quad_spi 50 50 100.00
spi_device_flash_all 256.320s 101037.887us 50 50 100.00
dual_spi 50 50 100.00
spi_device_flash_all 256.320s 101037.887us 50 50 100.00
4b_3b_feature 50 50 100.00
spi_device_cfg_cmd 21.630s 4032.594us 50 50 100.00
write_enable_disable 50 50 100.00
spi_device_cfg_cmd 21.630s 4032.594us 50 50 100.00
TPM_with_flash_or_passthrough_mode 50 50 100.00
spi_device_flash_and_tpm 395.140s 103155.428us 50 50 100.00
tpm_and_flash_trans_with_min_inactive_time 50 50 100.00
spi_device_flash_and_tpm_min_idle 491.440s 295501.336us 50 50 100.00
stress_all 50 50 100.00
spi_device_stress_all 800.040s 136274.809us 50 50 100.00
alert_test 50 50 100.00
spi_device_alert_test 1.110s 21.579us 50 50 100.00
intr_test 50 50 100.00
spi_device_intr_test 1.100s 107.613us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_device_tl_errors 5.280s 183.728us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_device_tl_errors 5.280s 183.728us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_device_csr_hw_reset 1.590s 81.546us 5 5 100.00
spi_device_csr_rw 2.910s 144.728us 20 20 100.00
spi_device_csr_aliasing 19.450s 14027.283us 5 5 100.00
spi_device_same_csr_outstanding 4.670s 617.193us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_device_csr_hw_reset 1.590s 81.546us 5 5 100.00
spi_device_csr_rw 2.910s 144.728us 20 20 100.00
spi_device_csr_aliasing 19.450s 14027.283us 5 5 100.00
spi_device_same_csr_outstanding 4.670s 617.193us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_device_tl_intg_err 24.530s 1057.086us 20 20 100.00
spi_device_sec_cm 1.700s 104.485us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
spi_device_tl_intg_err 24.530s 1057.086us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 49 50 98.00
spi_device_flash_mode_ignore_cmds 353.030s 284855.684us 49 50 98.00

Error Messages

   Test seed line log context
UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp *
spi_device_flash_mode_ignore_cmds 17575768993005136378069534541349803397442699939572376116920695691592514000020 88
UVM_ERROR @ 1358851495 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (16090112 [0xf58400] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0xf58400 != exp 0x0
tl_ul_fuzzy_flash_status_q[i] = 0x3f6004
tl_ul_fuzzy_flash_status_q[i] = 0xdb60ac
tl_ul_fuzzy_flash_status_q[i] = 0xdb60ae
UVM_INFO @ 1580301495 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 5/8