Simulation Results: spi_host

 
04/01/2026 00:13:51 sha: 05ff44d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.55 %
  • code
  • 95.02 %
  • assert
  • 95.21 %
  • func
  • 90.42 %
  • block
  • 96.82 %
  • line
  • 98.69 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
99.29%
V2
99.56%
V2S
100.00%
unmapped
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 49 50 98.00
spi_host_smoke 109.000s 48695.015us 49 50 98.00
csr_hw_reset 5 5 100.00
spi_host_csr_hw_reset 2.000s 39.886us 5 5 100.00
csr_rw 20 20 100.00
spi_host_csr_rw 2.000s 29.843us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_host_csr_bit_bash 4.000s 462.213us 5 5 100.00
csr_aliasing 5 5 100.00
spi_host_csr_aliasing 2.000s 71.626us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 30.429us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_host_csr_rw 2.000s 29.843us 20 20 100.00
spi_host_csr_aliasing 2.000s 71.626us 5 5 100.00
mem_walk 5 5 100.00
spi_host_mem_walk 1.000s 16.379us 5 5 100.00
mem_partial_access 5 5 100.00
spi_host_mem_partial_access 2.000s 30.475us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 50 50 100.00
spi_host_performance 2.000s 135.714us 50 50 100.00
error_event_intr 150 150 100.00
spi_host_overflow_underflow 83.000s 9081.769us 50 50 100.00
spi_host_error_cmd 2.000s 23.647us 50 50 100.00
spi_host_event 741.000s 107565.652us 50 50 100.00
clock_rate 50 50 100.00
spi_host_speed 8.000s 168.912us 50 50 100.00
speed 50 50 100.00
spi_host_speed 8.000s 168.912us 50 50 100.00
chip_select_timing 50 50 100.00
spi_host_speed 8.000s 168.912us 50 50 100.00
sw_reset 50 50 100.00
spi_host_sw_reset 134.000s 4601.693us 50 50 100.00
passthrough_mode 50 50 100.00
spi_host_passthrough_mode 2.000s 28.571us 50 50 100.00
cpol_cpha 50 50 100.00
spi_host_speed 8.000s 168.912us 50 50 100.00
full_cycle 50 50 100.00
spi_host_speed 8.000s 168.912us 50 50 100.00
duplex 49 50 98.00
spi_host_smoke 109.000s 48695.015us 49 50 98.00
tx_rx_only 49 50 98.00
spi_host_smoke 109.000s 48695.015us 49 50 98.00
stress_all 50 50 100.00
spi_host_stress_all 131.000s 3668.355us 50 50 100.00
spien 48 50 96.00
spi_host_spien 133.000s 75416.561us 48 50 96.00
stall 49 50 98.00
spi_host_status_stall 701.000s 118808.449us 49 50 98.00
Idlecsbactive 50 50 100.00
spi_host_idlecsbactive 34.000s 3796.284us 50 50 100.00
data_fifo_status 50 50 100.00
spi_host_overflow_underflow 83.000s 9081.769us 50 50 100.00
alert_test 50 50 100.00
spi_host_alert_test 2.000s 48.479us 50 50 100.00
intr_test 50 50 100.00
spi_host_intr_test 2.000s 15.164us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_host_tl_errors 4.000s 111.887us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_host_tl_errors 4.000s 111.887us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 39.886us 5 5 100.00
spi_host_csr_rw 2.000s 29.843us 20 20 100.00
spi_host_csr_aliasing 2.000s 71.626us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 27.155us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 39.886us 5 5 100.00
spi_host_csr_rw 2.000s 29.843us 20 20 100.00
spi_host_csr_aliasing 2.000s 71.626us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 27.155us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_host_sec_cm 2.000s 96.044us 5 5 100.00
spi_host_tl_intg_err 3.000s 345.472us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
spi_host_tl_intg_err 3.000s 345.472us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 9 10 90.00
spi_host_upper_range_clkdiv 561.000s 32862.749us 9 10 90.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_host_upper_range_clkdiv 62065831386821701385831116493746197950317684537123882756424612356187830920345 112
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=*
spi_host_spien 50472570058634588913711119935349454775117064956546049261924398919915775062460 305
UVM_FATAL @ 11042680105 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x2f071294, Comparison=CompareOpEq, exp_data=0x0, call_count=45
UVM_INFO @ 11042680105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_spien 35147771231651864912688429078011323884503360046698111046954604103117501952495 360
UVM_FATAL @ 11014682219 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0xc0a61c14, Comparison=CompareOpEq, exp_data=0x0, call_count=66
UVM_INFO @ 11014682219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=*
spi_host_smoke 4447419865856133240007784594866381827065148822773387805153415962808377421204 304
UVM_FATAL @ 48695014995 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 15000000ns spi_host_reg_block.status.active (addr=0x4a45c954, Comparison=CompareOpEq, exp_data=0x0, call_count=59
UVM_INFO @ 48695014995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: spi_host_reg_block.status.rxfull reset value: *
spi_host_status_stall 109193264424129772317918039584951114204616410009615018341680848990630440248396 1570
UVM_ERROR @ 1583926747 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_host_reg_block.status.rxfull reset value: 0x0
UVM_INFO @ 1583926747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---