Simulation Results: sram_ctrl

 
04/01/2026 00:13:51 sha: 05ff44d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.83 %
  • code
  • 96.15 %
  • assert
  • 95.83 %
  • func
  • 98.52 %
  • line
  • 99.11 %
  • branch
  • 98.02 %
  • cond
  • 92.90 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.97%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 92.260s 1549.816us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.060s 24.176us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.030s 39.003us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.260s 122.371us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.090s 66.738us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.870s 1199.499us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.030s 39.003us 20 20 100.00
sram_ctrl_csr_aliasing 1.090s 66.738us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 347.170s 19784.105us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 175.980s 24190.863us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1126.890s 45679.732us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 386.510s 8696.430us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 2408.390s 662910.769us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1288.320s 22353.614us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 120.270s 65699.768us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1586.770s 146114.150us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 110.090s 1978.426us 50 50 100.00
sram_ctrl_partial_access_b2b 644.190s 243222.296us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 103.000s 3187.508us 50 50 100.00
sram_ctrl_throughput_w_partial_write 97.410s 799.637us 50 50 100.00
sram_ctrl_throughput_w_readback 108.170s 1430.419us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1257.310s 7771.934us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 5.200s 1351.326us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 5787.330s 1954616.022us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.100s 141.328us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 4.940s 129.671us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 4.940s 129.671us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.060s 24.176us 5 5 100.00
sram_ctrl_csr_rw 1.030s 39.003us 20 20 100.00
sram_ctrl_csr_aliasing 1.090s 66.738us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.180s 90.572us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.060s 24.176us 5 5 100.00
sram_ctrl_csr_rw 1.030s 39.003us 20 20 100.00
sram_ctrl_csr_aliasing 1.090s 66.738us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.180s 90.572us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 67.980s 28125.635us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_sec_cm 1.010s 15.563us 0 5 0.00
sram_ctrl_tl_intg_err 3.300s 297.864us 20 20 100.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 1.010s 15.563us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 3.300s 297.864us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1257.310s 7771.934us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1257.310s 7771.934us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.030s 39.003us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1586.770s 146114.150us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1586.770s 146114.150us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1586.770s 146114.150us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 120.270s 65699.768us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 42 50 84.00
sram_ctrl_mubi_enc_err 9.440s 3151.575us 42 50 84.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 67.980s 28125.635us 20 20 100.00
sec_cm_mem_readback 41 50 82.00
sram_ctrl_readback_err 11.260s 13181.211us 41 50 82.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 92.260s 1549.816us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 92.260s 1549.816us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1586.770s 146114.150us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 1.010s 15.563us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 120.270s 65699.768us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 1.010s 15.563us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.010s 15.563us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 92.260s 1549.816us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.010s 15.563us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 419.450s 15084.341us 50 50 100.00

Error Messages

   Test seed line log context
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
sram_ctrl_sec_cm 72994064390426775430815395251689594847212070547309324067720948696376343121498 98
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR @ 3463330 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 3463330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 81839857767982229674840969622916804735027455400196618277407163995543715526456 97
UVM_ERROR @ 1757174 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 1757174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 71912591461342719653555348661883331733051752465360934347904491204393455617815 98
UVM_ERROR @ 15563164 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 15563164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 360665329961239498948693463382511459940938806764731517851198094722102251718 97
UVM_ERROR @ 3267542 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 3267542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 73428723718616107298131538910223923611988909372178905515630775633583951187125 97
UVM_ERROR @ 6700058 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 6700058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 96829759197221269639610576351461251179929076466691142624066610839245621256191 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 672038035 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 672038035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 44080818268398193733962977575339564150422051909037539466459246422448629858301 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2629564380 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2629564380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 82687285797448364488688105516418996662054876467175799300755846664493237880750 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 690115562 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 690115562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 47000969160198134382292013423837367817258283210204649685111443760930350929269 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 665740811 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 665740811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 63422123454264373407498793817013247747097980235884107195466036859614612348588 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2770007507 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2770007507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 33757016954925017667818103246271469412649951376595631104101851496574508758524 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 701396258 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 701396258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 57146095513706620398696066840525107041173372575066156845996411161051383187546 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 677275982 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 677275982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 84985862001325494210284475826470306793817646088915192744689924300018324303071 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 11202644566 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 11202644566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 8390080652059924624305871444137039979189386341733815538753079264953040940087 95
UVM_ERROR @ 685183457 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x29) != exp (0x4e)
UVM_INFO @ 685183457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 57119641585939075826812257125471416369944647507645146321333652880864264606629 95
UVM_ERROR @ 688044412 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x68) != exp (0x17)
UVM_INFO @ 688044412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 2930660434268051399547440497652416281634780577074241452345781101844873966862 95
UVM_ERROR @ 2752851731 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x30) != exp (0x2e)
UVM_INFO @ 2752851731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 401038757269964449406508674056017456899007767792372741802627347924571229179 95
UVM_ERROR @ 2737522498 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4d) != exp (0x20)
UVM_INFO @ 2737522498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 1115804180969589818330257610377472064931733849328598857660852833964949055071 95
UVM_ERROR @ 789766325 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1a) != exp (0x6a)
UVM_INFO @ 789766325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 3626856336652928545471510671281871776010944843199237460495926602052601182105 95
UVM_ERROR @ 691999616 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1a) != exp (0x77)
UVM_INFO @ 691999616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 77876460216512086926055718993310254714977253701281320236246079895361660604298 95
UVM_ERROR @ 722992022 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x9) != exp (0x5c)
UVM_INFO @ 722992022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 81932132045996375602289483576176770320523216810567938920021584625351587155863 95
UVM_ERROR @ 2994696216 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x54) != exp (0x63)
UVM_INFO @ 2994696216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 110255311319878085496766102271638143965431087223332881735063777607400592369660 95
UVM_ERROR @ 2529651144 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x35) != exp (0x5a)
UVM_INFO @ 2529651144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---