sram_ctrl Simulation Results

Simulation Results: sram_ctrl

04/01/2026 00:13:51 sha: 05ff44d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.75 %

code
96.12 %

assert
95.79 %

func
98.33 %

line
99.07 %

branch
97.98 %

cond
92.90 %

toggle
90.66 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		92.95%
V3		96.00%

230/230 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	sram_ctrl_smoke	104.960s	524.098us	50	50	100.00
csr_hw_reset				5	5	100.00
	sram_ctrl_csr_hw_reset	1.010s	25.334us	5	5	100.00
csr_rw				20	20	100.00
	sram_ctrl_csr_rw	1.020s	17.847us	20	20	100.00
csr_bit_bash				5	5	100.00
	sram_ctrl_csr_bit_bash	3.030s	686.432us	5	5	100.00
csr_aliasing				5	5	100.00
	sram_ctrl_csr_aliasing	1.030s	28.728us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	sram_ctrl_csr_mem_rw_with_rand_reset	2.720s	75.333us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	sram_ctrl_csr_rw	1.020s	17.847us	20	20	100.00
	sram_ctrl_csr_aliasing	1.030s	28.728us	5	5	100.00
mem_walk				50	50	100.00
	sram_ctrl_mem_walk	14.540s	2743.648us	50	50	100.00
mem_partial_access				50	50	100.00
	sram_ctrl_mem_partial_access	6.590s	672.360us	50	50	100.00

890/890 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
multiple_keys				50	50	100.00
	sram_ctrl_multiple_keys	1159.510s	79289.924us	50	50	100.00
stress_pipeline				50	50	100.00
	sram_ctrl_stress_pipeline	345.990s	23245.387us	50	50	100.00
bijection				50	50	100.00
	sram_ctrl_bijection	85.550s	21667.079us	50	50	100.00
access_during_key_req				50	50	100.00
	sram_ctrl_access_during_key_req	1186.110s	18665.814us	50	50	100.00
lc_escalation				50	50	100.00
	sram_ctrl_lc_escalation	12.700s	935.801us	50	50	100.00
executable				50	50	100.00
	sram_ctrl_executable	1313.140s	57152.635us	50	50	100.00
partial_access				100	100	100.00
	sram_ctrl_partial_access	93.250s	6370.507us	50	50	100.00
	sram_ctrl_partial_access_b2b	498.780s	92931.335us	50	50	100.00
max_throughput				150	150	100.00
	sram_ctrl_max_throughput	95.090s	265.997us	50	50	100.00
	sram_ctrl_throughput_w_partial_write	98.050s	584.461us	50	50	100.00
	sram_ctrl_throughput_w_readback	106.020s	1277.848us	50	50	100.00
regwen				50	50	100.00
	sram_ctrl_regwen	1140.330s	40053.625us	50	50	100.00
ram_cfg				50	50	100.00
	sram_ctrl_ram_cfg	1.190s	238.271us	50	50	100.00
stress_all				50	50	100.00
	sram_ctrl_stress_all	3834.820s	857250.212us	50	50	100.00
alert_test				50	50	100.00
	sram_ctrl_alert_test	1.060s	48.121us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	sram_ctrl_tl_errors	5.200s	312.570us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	sram_ctrl_tl_errors	5.200s	312.570us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	sram_ctrl_csr_hw_reset	1.010s	25.334us	5	5	100.00
	sram_ctrl_csr_rw	1.020s	17.847us	20	20	100.00
	sram_ctrl_csr_aliasing	1.030s	28.728us	5	5	100.00
	sram_ctrl_same_csr_outstanding	1.090s	24.801us	20	20	100.00
tl_d_partial_access				50	50	100.00
	sram_ctrl_csr_hw_reset	1.010s	25.334us	5	5	100.00
	sram_ctrl_csr_rw	1.020s	17.847us	20	20	100.00
	sram_ctrl_csr_aliasing	1.030s	28.728us	5	5	100.00
	sram_ctrl_same_csr_outstanding	1.090s	24.801us	20	20	100.00

V2S

725/780 passed

92.95 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
passthru_mem_tl_intg_err				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	3.730s	1653.646us	20	20	100.00
tl_intg_err				20	25	80.00
	sram_ctrl_sec_cm	1.160s	6.772us	0	5	0.00
	sram_ctrl_tl_intg_err	3.520s	324.939us	20	20	100.00
prim_count_check				0	5	0.00
	sram_ctrl_sec_cm	1.160s	6.772us	0	5	0.00
sec_cm_bus_integrity				20	20	100.00
	sram_ctrl_tl_intg_err	3.520s	324.939us	20	20	100.00
sec_cm_ctrl_config_regwen				50	50	100.00
	sram_ctrl_regwen	1140.330s	40053.625us	50	50	100.00
sec_cm_readback_config_regwen				50	50	100.00
	sram_ctrl_regwen	1140.330s	40053.625us	50	50	100.00
sec_cm_exec_config_regwen				20	20	100.00
	sram_ctrl_csr_rw	1.020s	17.847us	20	20	100.00
sec_cm_exec_config_mubi				50	50	100.00
	sram_ctrl_executable	1313.140s	57152.635us	50	50	100.00
sec_cm_exec_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1313.140s	57152.635us	50	50	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1313.140s	57152.635us	50	50	100.00
sec_cm_lc_escalate_en_intersig_mubi				50	50	100.00
	sram_ctrl_lc_escalation	12.700s	935.801us	50	50	100.00
sec_cm_prim_ram_ctrl_mubi				42	50	84.00
	sram_ctrl_mubi_enc_err	1.690s	104.075us	42	50	84.00
sec_cm_mem_integrity				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	3.730s	1653.646us	20	20	100.00
sec_cm_mem_readback				33	50	66.00
	sram_ctrl_readback_err	1.690s	49.107us	33	50	66.00
sec_cm_mem_scramble				50	50	100.00
	sram_ctrl_smoke	104.960s	524.098us	50	50	100.00
sec_cm_addr_scramble				50	50	100.00
	sram_ctrl_smoke	104.960s	524.098us	50	50	100.00
sec_cm_instr_bus_lc_gated				50	50	100.00
	sram_ctrl_executable	1313.140s	57152.635us	50	50	100.00
sec_cm_ram_tl_lc_gate_fsm_sparse				0	5	0.00
	sram_ctrl_sec_cm	1.160s	6.772us	0	5	0.00
sec_cm_key_global_esc				50	50	100.00
	sram_ctrl_lc_escalation	12.700s	935.801us	50	50	100.00
sec_cm_key_local_esc				0	5	0.00
	sram_ctrl_sec_cm	1.160s	6.772us	0	5	0.00
sec_cm_init_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	1.160s	6.772us	0	5	0.00
sec_cm_scramble_key_sideload				50	50	100.00
	sram_ctrl_smoke	104.960s	524.098us	50	50	100.00
sec_cm_tlul_fifo_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	1.160s	6.772us	0	5	0.00

48/50 passed

96.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				48	50	96.00
	sram_ctrl_stress_all_with_rand_reset	763.860s	5543.246us	48	50	96.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act () != exp ()
	sram_ctrl_readback_err	37435404144212357865053155245745703427442675940477369513874338404492992160711	95	UVM_ERROR @ 56441869 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4c) != exp (0x26) UVM_INFO @ 56441869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	33340283093857649003081829811440387482957392450384965047640682263579903026310	95	UVM_ERROR @ 170013103 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6c) != exp (0x76) UVM_INFO @ 170013103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	44886765581631323835135013027674154854784284690365640243699008602211580292919	95	UVM_ERROR @ 24949167 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x33) != exp (0x24) UVM_INFO @ 24949167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	73960896445188250820924696971121517671079633658980608041905798066513825454853	95	UVM_ERROR @ 130635731 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x14) != exp (0x73) UVM_INFO @ 130635731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	14174374324118333958371503091315790547236966439023021116206452858189851889382	95	UVM_ERROR @ 26617980 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x40) != exp (0x7d) UVM_INFO @ 26617980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	44215649465008871710412482125187452791483259426384396430771110810062440430100	95	UVM_ERROR @ 107024914 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1a) != exp (0xf) UVM_INFO @ 107024914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	115383463319150625204291276131428855036571210942475353144175563998785761725810	95	UVM_ERROR @ 39347924 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x26) != exp (0x51) UVM_INFO @ 39347924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	36093011137149194107463439314729896234864326633094689643508073625508753464602	95	UVM_ERROR @ 25367384 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x17) != exp (0x4c) UVM_INFO @ 25367384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	113940089800664413943050560176051458508730788617320950548727741432567760091750	95	UVM_ERROR @ 26185397 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2b) != exp (0x7b) UVM_INFO @ 26185397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	59207098059243461200664452616717956660411211778415260416084362039547863915140	95	UVM_ERROR @ 58575742 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x19) != exp (0x7e) UVM_INFO @ 58575742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	3857621027536071841973156148496522573225531687611120693615144108478436869930	95	UVM_ERROR @ 188560410 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7a) != exp (0x1b) UVM_INFO @ 188560410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	90656942588277372674620015804660678696171872064828732269928689370893132123778	95	UVM_ERROR @ 78416626 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6e) != exp (0x69) UVM_INFO @ 78416626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	40745087910196221040794351543054254188074671124154654086430517364173427182829	95	UVM_ERROR @ 37042525 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x47) != exp (0x76) UVM_INFO @ 37042525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	12962313593804522731339385063826843672714300853129799412743576808674287083221	95	UVM_ERROR @ 27296668 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x76) != exp (0x2f) UVM_INFO @ 27296668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	101831952305032548010984747900277766395061495091347497535829641161134257366305	95	UVM_ERROR @ 315059337 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x41) != exp (0x2e) UVM_INFO @ 315059337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	1727695029784434019968924959145228060941037773439176276779290041487454777407	95	UVM_ERROR @ 30035516 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x65) != exp (0x38) UVM_INFO @ 30035516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	51679550499298887973754919007319754003279825690238153762399252089379018775657	95	UVM_ERROR @ 451573065 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x34) != exp (0x72) UVM_INFO @ 451573065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.status.init_error reset value:
	sram_ctrl_sec_cm	23273366675805208337028834201018537750662768808532450786644628078309483483104	99	UVM_ERROR @ 20790800 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 20790800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	35040228867356815504714208391129198094308380199185902532079820455587867835628	96	UVM_ERROR @ 4256540 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 4256540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(depth_o <= *'(Depth))'
	sram_ctrl_sec_cm	63196972534633973944162504950274814307094868559951144158719709224615003380068	96	Offending '(depth_o <= 2'(Depth))' UVM_ERROR @ 5435842 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth UVM_INFO @ 5435842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	70381759218847500226873047223924085622691990701869063282434737778713878909345	98	Offending '(depth_o <= 2'(Depth))' UVM_ERROR @ 6772029 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth UVM_INFO @ 6772029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
	sram_ctrl_mubi_enc_err	29467564912699012245273894600889981440694912644312154351018649824231518480524	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 51671208 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 51671208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	101212485447181075619884631766434482291434827928210352770708534033339914889633	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 67532951 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 67532951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	16420468332004905924806396912473455163375011665138008265269538370101285504264	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 28640757 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 28640757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	61315595591045516846887741043388616577787991005181789425393354108030238868069	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 251771609 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 251771609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	72477629277095216860787441539992336599632487384305991310433549966772805079041	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 23621156 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 23621156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	39543524421513785787071160477719807076795100001569387675549632981595130824998	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 130430244 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 130430244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	13620167880725878969288294305396775511573797542731464198625665187585171659961	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 67125680 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 67125680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	111984177984856403756757310521294123033594457914367283415597277485641359586550	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 36917527 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 36917527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
	sram_ctrl_sec_cm	77836225126344542284513221745728805051556729894575882402281178828031377577606	96	Offending '(!$isunknown(rdata_o))' UVM_ERROR @ 1927713 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A UVM_INFO @ 1927713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	sram_ctrl_stress_all_with_rand_reset	41846841308074442760789216843400553396107958670032661253401970038618884578149	294	UVM_ERROR @ 1066914431 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 1066914431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_stress_all_with_rand_reset	50821866206273443179275509317542982179224591875690428928764850793234705736869	131	UVM_ERROR @ 1876159589 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 1876159589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---