| V1 |
|
100.00% |
| V2 |
|
99.85% |
| V2S |
|
96.20% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wake_up | 1 | 1 | 100.00 | |||
| aes_wake_up | 6.000s | 379.072us | 1 | 1 | 100.00 | |
| smoke | 50 | 50 | 100.00 | |||
| aes_smoke | 6.000s | 150.998us | 50 | 50 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| aes_csr_hw_reset | 3.000s | 89.929us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| aes_csr_rw | 2.000s | 111.712us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| aes_csr_bit_bash | 7.000s | 3327.392us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| aes_csr_aliasing | 3.000s | 310.207us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| aes_csr_mem_rw_with_rand_reset | 2.000s | 106.686us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| aes_csr_rw | 2.000s | 111.712us | 20 | 20 | 100.00 | |
| aes_csr_aliasing | 3.000s | 310.207us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| algorithm | 150 | 150 | 100.00 | |||
| aes_smoke | 6.000s | 150.998us | 50 | 50 | 100.00 | |
| aes_config_error | 20.000s | 806.892us | 50 | 50 | 100.00 | |
| aes_stress | 41.000s | 3476.050us | 50 | 50 | 100.00 | |
| key_length | 150 | 150 | 100.00 | |||
| aes_smoke | 6.000s | 150.998us | 50 | 50 | 100.00 | |
| aes_config_error | 20.000s | 806.892us | 50 | 50 | 100.00 | |
| aes_stress | 41.000s | 3476.050us | 50 | 50 | 100.00 | |
| back2back | 100 | 100 | 100.00 | |||
| aes_stress | 41.000s | 3476.050us | 50 | 50 | 100.00 | |
| aes_b2b | 34.000s | 551.521us | 50 | 50 | 100.00 | |
| backpressure | 50 | 50 | 100.00 | |||
| aes_stress | 41.000s | 3476.050us | 50 | 50 | 100.00 | |
| multi_message | 200 | 200 | 100.00 | |||
| aes_smoke | 6.000s | 150.998us | 50 | 50 | 100.00 | |
| aes_config_error | 20.000s | 806.892us | 50 | 50 | 100.00 | |
| aes_stress | 41.000s | 3476.050us | 50 | 50 | 100.00 | |
| aes_alert_reset | 56.000s | 2702.533us | 50 | 50 | 100.00 | |
| failure_test | 148 | 150 | 98.67 | |||
| aes_man_cfg_err | 6.000s | 231.286us | 48 | 50 | 96.00 | |
| aes_config_error | 20.000s | 806.892us | 50 | 50 | 100.00 | |
| aes_alert_reset | 56.000s | 2702.533us | 50 | 50 | 100.00 | |
| trigger_clear_test | 50 | 50 | 100.00 | |||
| aes_clear | 12.000s | 968.478us | 50 | 50 | 100.00 | |
| nist_test_vectors | 1 | 1 | 100.00 | |||
| aes_nist_vectors | 8.000s | 3012.368us | 1 | 1 | 100.00 | |
| reset_recovery | 50 | 50 | 100.00 | |||
| aes_alert_reset | 56.000s | 2702.533us | 50 | 50 | 100.00 | |
| stress | 50 | 50 | 100.00 | |||
| aes_stress | 41.000s | 3476.050us | 50 | 50 | 100.00 | |
| sideload | 100 | 100 | 100.00 | |||
| aes_stress | 41.000s | 3476.050us | 50 | 50 | 100.00 | |
| aes_sideload | 24.000s | 971.979us | 50 | 50 | 100.00 | |
| deinitialization | 50 | 50 | 100.00 | |||
| aes_deinit | 7.000s | 113.510us | 50 | 50 | 100.00 | |
| stress_all | 10 | 10 | 100.00 | |||
| aes_stress_all | 63.000s | 2128.090us | 10 | 10 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| aes_alert_test | 3.000s | 67.661us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| aes_tl_errors | 3.000s | 291.749us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| aes_tl_errors | 3.000s | 291.749us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| aes_csr_hw_reset | 3.000s | 89.929us | 5 | 5 | 100.00 | |
| aes_csr_rw | 2.000s | 111.712us | 20 | 20 | 100.00 | |
| aes_csr_aliasing | 3.000s | 310.207us | 5 | 5 | 100.00 | |
| aes_same_csr_outstanding | 3.000s | 100.269us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| aes_csr_hw_reset | 3.000s | 89.929us | 5 | 5 | 100.00 | |
| aes_csr_rw | 2.000s | 111.712us | 20 | 20 | 100.00 | |
| aes_csr_aliasing | 3.000s | 310.207us | 5 | 5 | 100.00 | |
| aes_same_csr_outstanding | 3.000s | 100.269us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reseeding | 50 | 50 | 100.00 | |||
| aes_reseed | 73.000s | 3102.071us | 50 | 50 | 100.00 | |
| fault_inject | 668 | 700 | 95.43 | |||
| aes_fi | 13.000s | 1051.550us | 50 | 50 | 100.00 | |
| aes_control_fi | 59.000s | 10004.739us | 280 | 300 | 93.33 | |
| aes_cipher_fi | 58.000s | 10070.980us | 338 | 350 | 96.57 | |
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 152.830us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 152.830us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 152.830us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 152.830us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors_with_csr_rw | 4.000s | 199.840us | 20 | 20 | 100.00 | |
| tl_intg_err | 25 | 25 | 100.00 | |||
| aes_tl_intg_err | 3.000s | 204.624us | 20 | 20 | 100.00 | |
| aes_sec_cm | 8.000s | 1024.748us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| aes_tl_intg_err | 3.000s | 204.624us | 20 | 20 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 50 | 50 | 100.00 | |||
| aes_alert_reset | 56.000s | 2702.533us | 50 | 50 | 100.00 | |
| sec_cm_main_config_shadow | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 152.830us | 20 | 20 | 100.00 | |
| sec_cm_gcm_config_shadow | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 152.830us | 20 | 20 | 100.00 | |
| sec_cm_main_config_sparse | 218 | 220 | 99.09 | |||
| aes_smoke | 6.000s | 150.998us | 50 | 50 | 100.00 | |
| aes_stress | 41.000s | 3476.050us | 50 | 50 | 100.00 | |
| aes_alert_reset | 56.000s | 2702.533us | 50 | 50 | 100.00 | |
| aes_core_fi | 64.000s | 10003.309us | 68 | 70 | 97.14 | |
| sec_cm_gcm_config_sparse | 100 | 100 | 100.00 | |||
| aes_config_error | 20.000s | 806.892us | 50 | 50 | 100.00 | |
| aes_stress | 41.000s | 3476.050us | 50 | 50 | 100.00 | |
| sec_cm_aux_config_shadow | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 3.000s | 152.830us | 20 | 20 | 100.00 | |
| sec_cm_aux_config_regwen | 100 | 100 | 100.00 | |||
| aes_readability | 4.000s | 399.778us | 50 | 50 | 100.00 | |
| aes_stress | 41.000s | 3476.050us | 50 | 50 | 100.00 | |
| sec_cm_key_sideload | 100 | 100 | 100.00 | |||
| aes_stress | 41.000s | 3476.050us | 50 | 50 | 100.00 | |
| aes_sideload | 24.000s | 971.979us | 50 | 50 | 100.00 | |
| sec_cm_key_sw_unreadable | 50 | 50 | 100.00 | |||
| aes_readability | 4.000s | 399.778us | 50 | 50 | 100.00 | |
| sec_cm_data_reg_sw_unreadable | 50 | 50 | 100.00 | |||
| aes_readability | 4.000s | 399.778us | 50 | 50 | 100.00 | |
| sec_cm_key_sec_wipe | 50 | 50 | 100.00 | |||
| aes_readability | 4.000s | 399.778us | 50 | 50 | 100.00 | |
| sec_cm_iv_config_sec_wipe | 50 | 50 | 100.00 | |||
| aes_readability | 4.000s | 399.778us | 50 | 50 | 100.00 | |
| sec_cm_data_reg_sec_wipe | 50 | 50 | 100.00 | |||
| aes_readability | 4.000s | 399.778us | 50 | 50 | 100.00 | |
| sec_cm_data_reg_key_sca | 50 | 50 | 100.00 | |||
| aes_stress | 41.000s | 3476.050us | 50 | 50 | 100.00 | |
| sec_cm_key_masking | 50 | 50 | 100.00 | |||
| aes_stress | 41.000s | 3476.050us | 50 | 50 | 100.00 | |
| sec_cm_main_fsm_sparse | 50 | 50 | 100.00 | |||
| aes_fi | 13.000s | 1051.550us | 50 | 50 | 100.00 | |
| sec_cm_main_fsm_redun | 716 | 750 | 95.47 | |||
| aes_fi | 13.000s | 1051.550us | 50 | 50 | 100.00 | |
| aes_control_fi | 59.000s | 10004.739us | 280 | 300 | 93.33 | |
| aes_cipher_fi | 58.000s | 10070.980us | 338 | 350 | 96.57 | |
| aes_ctr_fi | 55.000s | 10023.393us | 48 | 50 | 96.00 | |
| sec_cm_cipher_fsm_sparse | 50 | 50 | 100.00 | |||
| aes_fi | 13.000s | 1051.550us | 50 | 50 | 100.00 | |
| sec_cm_cipher_fsm_redun | 668 | 700 | 95.43 | |||
| aes_fi | 13.000s | 1051.550us | 50 | 50 | 100.00 | |
| aes_control_fi | 59.000s | 10004.739us | 280 | 300 | 93.33 | |
| aes_cipher_fi | 58.000s | 10070.980us | 338 | 350 | 96.57 | |
| sec_cm_cipher_ctr_redun | 338 | 350 | 96.57 | |||
| aes_cipher_fi | 58.000s | 10070.980us | 338 | 350 | 96.57 | |
| sec_cm_ctr_fsm_sparse | 50 | 50 | 100.00 | |||
| aes_fi | 13.000s | 1051.550us | 50 | 50 | 100.00 | |
| sec_cm_ctr_fsm_redun | 378 | 400 | 94.50 | |||
| aes_fi | 13.000s | 1051.550us | 50 | 50 | 100.00 | |
| aes_control_fi | 59.000s | 10004.739us | 280 | 300 | 93.33 | |
| aes_ctr_fi | 55.000s | 10023.393us | 48 | 50 | 96.00 | |
| sec_cm_ctrl_sparse | 716 | 750 | 95.47 | |||
| aes_fi | 13.000s | 1051.550us | 50 | 50 | 100.00 | |
| aes_control_fi | 59.000s | 10004.739us | 280 | 300 | 93.33 | |
| aes_cipher_fi | 58.000s | 10070.980us | 338 | 350 | 96.57 | |
| aes_ctr_fi | 55.000s | 10023.393us | 48 | 50 | 96.00 | |
| sec_cm_main_fsm_global_esc | 50 | 50 | 100.00 | |||
| aes_alert_reset | 56.000s | 2702.533us | 50 | 50 | 100.00 | |
| sec_cm_main_fsm_local_esc | 716 | 750 | 95.47 | |||
| aes_fi | 13.000s | 1051.550us | 50 | 50 | 100.00 | |
| aes_control_fi | 59.000s | 10004.739us | 280 | 300 | 93.33 | |
| aes_cipher_fi | 58.000s | 10070.980us | 338 | 350 | 96.57 | |
| aes_ctr_fi | 55.000s | 10023.393us | 48 | 50 | 96.00 | |
| sec_cm_cipher_fsm_local_esc | 716 | 750 | 95.47 | |||
| aes_fi | 13.000s | 1051.550us | 50 | 50 | 100.00 | |
| aes_control_fi | 59.000s | 10004.739us | 280 | 300 | 93.33 | |
| aes_cipher_fi | 58.000s | 10070.980us | 338 | 350 | 96.57 | |
| aes_ctr_fi | 55.000s | 10023.393us | 48 | 50 | 96.00 | |
| sec_cm_ctr_fsm_local_esc | 378 | 400 | 94.50 | |||
| aes_fi | 13.000s | 1051.550us | 50 | 50 | 100.00 | |
| aes_control_fi | 59.000s | 10004.739us | 280 | 300 | 93.33 | |
| aes_ctr_fi | 55.000s | 10023.393us | 48 | 50 | 96.00 | |
| sec_cm_data_reg_local_esc | 668 | 700 | 95.43 | |||
| aes_fi | 13.000s | 1051.550us | 50 | 50 | 100.00 | |
| aes_control_fi | 59.000s | 10004.739us | 280 | 300 | 93.33 | |
| aes_cipher_fi | 58.000s | 10070.980us | 338 | 350 | 96.57 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 10 | 0.00 | |||
| aes_stress_all_with_rand_reset | 20.000s | 346.242us | 0 | 10 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! | ||||
| aes_core_fi | 17750260577639859666541708656150326540012747724277424997002683860233185907535 | 146 |
UVM_FATAL @ 10003309391 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10003309391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_core_fi | 51043491032391358476457288344063649859533499235554072596872168379905784059817 | 147 |
UVM_FATAL @ 10002650018 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
UVM_INFO @ 10002650018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) | ||||
| aes_stress_all_with_rand_reset | 45382062710817494098502986539054020788000802798893772946763720219111779918810 | 270 |
UVM_FATAL @ 1764823848 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 1764823848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all_with_rand_reset | 98600961928326789316428855952350153801870395860087191031802194572941230779847 | 320 |
UVM_FATAL @ 915599570 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 915599570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | ||||
| aes_stress_all_with_rand_reset | 72871617574456884598215419602868691753093791716428767322142269633106385911826 | 104 |
UVM_ERROR @ 120048418 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 120048418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all_with_rand_reset | 63944362247320890244268607308796535108336283561220111688277384154691834099219 | 437 |
UVM_ERROR @ 379121351 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 379121351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! | ||||
| aes_cipher_fi | 20239981655780873033061586309426679193491226962912888666253450244810874986604 | 138 |
UVM_FATAL @ 10014764205 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10014764205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 43879758219214323817880790182053737880862268118298803948291173906377216569162 | 136 |
UVM_FATAL @ 10070979751 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10070979751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 47603705159795065844992116143609514496129962827906549285496351122852179990039 | 139 |
UVM_FATAL @ 10031430800 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10031430800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 114486586584398475719117778500897736434979759468413137887037754274502446193526 | 145 |
UVM_FATAL @ 10011628156 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10011628156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 88347793811777690421607494947969355666224314685841779332783794678950930419272 | 143 |
UVM_FATAL @ 10014449853 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10014449853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 61878392923864123459886245106330250759182080285427310072548939969835611577930 | 132 |
UVM_FATAL @ 10015003277 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10015003277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 114973975245654952457559111979837522458365079530871872110031703437298278335891 | 143 |
UVM_FATAL @ 10007943165 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10007943165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 40456778515106061920948037048855742262629842998326539002189642837578284497753 | 148 |
UVM_FATAL @ 10007254057 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10007254057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 21969985298747384427552086759361515151475950499181222833053597217967162392314 | 142 |
UVM_FATAL @ 10016755041 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10016755041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 83877903649333339329105850962933506274779380250500688966374586352311237451541 | 136 |
UVM_FATAL @ 10007571117 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10007571117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 101645191090675548263706051671867542334640664151464471678622582004784251142453 | 139 |
UVM_FATAL @ 10012236076 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10012236076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) | ||||
| aes_stress_all_with_rand_reset | 86208626437083399595674400229665002239495803792453046473994879777137878473627 | 158 |
UVM_FATAL @ 67523572 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 67523572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all_with_rand_reset | 98304798731074086716425351727925475585203160176430096996547955258764719642786 | 160 |
UVM_FATAL @ 93088014 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 93088014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all_with_rand_reset | 101353077184081927002053988589528873891502927553689986965573796039802486857928 | 186 |
UVM_FATAL @ 72525428 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 72525428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) | ||||
| aes_stress_all_with_rand_reset | 74413236915916620819199639219958424617974841904119676014253280556655875054753 | 159 |
UVM_FATAL @ 108345275 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 108345275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | ||||
| aes_stress_all_with_rand_reset | 41252774753923288916660507466838179482985199656216887719313314045073366674004 | 583 |
UVM_ERROR @ 500636087 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 500636087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all_with_rand_reset | 59027019163648378236925390256946208825834036402349238335076844644180617463238 | 430 |
UVM_ERROR @ 346242423 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 346242423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! | ||||
| aes_control_fi | 29502272527369723759311057250741563962203095802250678828791736185011424200261 | 139 |
UVM_FATAL @ 10025652483 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10025652483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 25654712302472890675549625638340166319972078223578670744509461381469785510303 | 141 |
UVM_FATAL @ 10013700947 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10013700947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 106982153611900805700366819323728107459348137859692424330683311506709492317731 | 139 |
UVM_FATAL @ 10020377061 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10020377061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 42476447732744642832951222760475437217602657583221134127674739021220507390868 | 139 |
UVM_FATAL @ 10010602371 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10010602371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 101575525516462383783346760273956831365683227660252285970700927892224941402430 | 143 |
UVM_FATAL @ 10023266501 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10023266501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 90663031920989114053531279259188275800470123396367507422718933313352496960192 | 136 |
UVM_FATAL @ 10003345759 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10003345759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 68968947778888824115644519640421678639750792755915299717773363172004754397416 | 139 |
UVM_FATAL @ 10016913123 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10016913123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 44145341195788265884986218863064856113362402017529760334310441847464878540183 | 141 |
UVM_FATAL @ 10004738649 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10004738649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 37254810824102609848908074520043286957092361003543728485195163263493613546503 | 135 |
UVM_FATAL @ 10004063469 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10004063469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 98937704350837837608978354425656500523846954350476354749888411002636775385535 | 144 |
UVM_FATAL @ 10002883122 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10002883122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (aes_manual_config_err_vseq.sv:71) virtual_sequencer [aes_manual_config_err_vseq] WAS ABLE TO TRIGGER OPERATION WITH ILLEGAL MODE | ||||
| aes_man_cfg_err | 49395968852034908168213172715813898638039609404267716098893245690804135462406 | 133 |
UVM_FATAL @ 6449399 ps: (aes_manual_config_err_vseq.sv:71) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_manual_config_err_vseq] WAS ABLE TO TRIGGER OPERATION WITH ILLEGAL MODE
UVM_INFO @ 6449399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_man_cfg_err | 105495103235215935125370558283072502930969021946751211523320286190894131026050 | 133 |
UVM_FATAL @ 6180403 ps: (aes_manual_config_err_vseq.sv:71) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_manual_config_err_vseq] WAS ABLE TO TRIGGER OPERATION WITH ILLEGAL MODE
UVM_INFO @ 6180403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | ||||
| aes_control_fi | 42785276359088999416599731145742678028886629101297693458440272549502978001593 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 17082129643621923928934378270866508550704005780599632883940068244349754119107 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 5114159070105518906129304164470899965886407147141658365664645303719767039245 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 110120777654575407642562907884892865381693665175201069312028447329893871155672 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 86055609671820582280447682482940685230388201185459992048345316418065410503632 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 75780546468457607476358478269713754442699215156622591228294047323951189757248 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 52652870559686375630367917516283998956567135401417488980466445492237804281999 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 89465015724077767368290883302379352711097472039837268355884723523699206172048 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 48724969300829165180665892221097310908661756899394448895951930315360363903851 | None |
Job timed out after 1 minutes
|
|
| aes_control_fi | 67405853879744769514031778280267589960047357374426453939414053511869238876602 | None |
Job timed out after 1 minutes
|
|
| UVM_FATAL (aes_ctr_fi_vseq.sv:59) [aes_ctr_fi_vseq] wait timeout occurred! | ||||
| aes_ctr_fi | 62271632488733014971744735505631513154530501159247146106754014760959015649846 | 132 |
UVM_FATAL @ 10023392501 ps: (aes_ctr_fi_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.aes_ctr_fi_vseq] wait timeout occurred!
UVM_INFO @ 10023392501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_ctr_fi | 8198919745439056518725337525608896210261920033979743851105271042913178047042 | 138 |
UVM_FATAL @ 10008860109 ps: (aes_ctr_fi_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.aes_ctr_fi_vseq] wait timeout occurred!
UVM_INFO @ 10008860109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) | ||||
| aes_cipher_fi | 59994625819110236986354778955688165240637665579473571118488187024719830810505 | 129 |
UVM_FATAL @ 10020270996 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0xea9bd84, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10020270996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|