Simulation Results: clkmgr

 
11/01/2026 00:07:26 sha: 8eebaba json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.24 %
  • code
  • 99.01 %
  • assert
  • 95.90 %
  • func
  • 87.82 %
  • line
  • 99.38 %
  • branch
  • 99.27 %
  • cond
  • 96.38 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
97.78%
V3
99.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
clkmgr_smoke 1.580s 378.869us 50 50 100.00
csr_hw_reset 5 5 100.00
clkmgr_csr_hw_reset 0.890s 22.800us 5 5 100.00
csr_rw 20 20 100.00
clkmgr_csr_rw 1.120s 215.228us 20 20 100.00
csr_bit_bash 5 5 100.00
clkmgr_csr_bit_bash 5.710s 432.641us 5 5 100.00
csr_aliasing 5 5 100.00
clkmgr_csr_aliasing 1.840s 92.645us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.670s 271.009us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
clkmgr_csr_rw 1.120s 215.228us 20 20 100.00
clkmgr_csr_aliasing 1.840s 92.645us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 50 50 100.00
clkmgr_peri 1.120s 29.069us 50 50 100.00
trans_enables 50 50 100.00
clkmgr_trans 2.360s 429.695us 50 50 100.00
extclk 50 50 100.00
clkmgr_extclk 1.390s 74.712us 50 50 100.00
clk_status 50 50 100.00
clkmgr_clk_status 1.190s 162.156us 50 50 100.00
jitter 50 50 100.00
clkmgr_smoke 1.580s 378.869us 50 50 100.00
frequency 50 50 100.00
clkmgr_frequency 11.880s 2244.873us 50 50 100.00
frequency_timeout 50 50 100.00
clkmgr_frequency_timeout 12.620s 2417.643us 50 50 100.00
frequency_overflow 50 50 100.00
clkmgr_frequency 11.880s 2244.873us 50 50 100.00
stress_all 50 50 100.00
clkmgr_stress_all 49.510s 10011.897us 50 50 100.00
alert_test 50 50 100.00
clkmgr_alert_test 1.320s 234.501us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
clkmgr_tl_errors 2.830s 448.564us 20 20 100.00
tl_d_illegal_access 20 20 100.00
clkmgr_tl_errors 2.830s 448.564us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
clkmgr_csr_hw_reset 0.890s 22.800us 5 5 100.00
clkmgr_csr_rw 1.120s 215.228us 20 20 100.00
clkmgr_csr_aliasing 1.840s 92.645us 5 5 100.00
clkmgr_same_csr_outstanding 1.870s 410.654us 20 20 100.00
tl_d_partial_access 50 50 100.00
clkmgr_csr_hw_reset 0.890s 22.800us 5 5 100.00
clkmgr_csr_rw 1.120s 215.228us 20 20 100.00
clkmgr_csr_aliasing 1.840s 92.645us 5 5 100.00
clkmgr_same_csr_outstanding 1.870s 410.654us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 21 25 84.00
clkmgr_sec_cm 3.450s 1059.780us 1 5 20.00
clkmgr_tl_intg_err 3.670s 1000.171us 20 20 100.00
shadow_reg_update_error 20 20 100.00
clkmgr_shadow_reg_errors 2.090s 394.843us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
clkmgr_shadow_reg_errors 2.090s 394.843us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
clkmgr_shadow_reg_errors 2.090s 394.843us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
clkmgr_shadow_reg_errors 2.090s 394.843us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
clkmgr_shadow_reg_errors_with_csr_rw 3.890s 632.484us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
clkmgr_tl_intg_err 3.670s 1000.171us 20 20 100.00
sec_cm_meas_clk_bkgn_chk 50 50 100.00
clkmgr_frequency 11.880s 2244.873us 50 50 100.00
sec_cm_timeout_clk_bkgn_chk 50 50 100.00
clkmgr_frequency_timeout 12.620s 2417.643us 50 50 100.00
sec_cm_meas_config_shadow 20 20 100.00
clkmgr_shadow_reg_errors 2.090s 394.843us 20 20 100.00
sec_cm_idle_intersig_mubi 50 50 100.00
clkmgr_idle_intersig_mubi 1.910s 424.284us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
clkmgr_lc_ctrl_intersig_mubi 1.670s 225.169us 50 50 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 50 50 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.330s 115.472us 50 50 100.00
sec_cm_clk_handshake_intersig_mubi 49 50 98.00
clkmgr_clk_handshake_intersig_mubi 1.500s 209.251us 49 50 98.00
sec_cm_div_intersig_mubi 50 50 100.00
clkmgr_div_intersig_mubi 1.160s 77.443us 50 50 100.00
sec_cm_jitter_config_mubi 20 20 100.00
clkmgr_csr_rw 1.120s 215.228us 20 20 100.00
sec_cm_idle_ctr_redun 1 5 20.00
clkmgr_sec_cm 3.450s 1059.780us 1 5 20.00
sec_cm_meas_config_regwen 20 20 100.00
clkmgr_csr_rw 1.120s 215.228us 20 20 100.00
sec_cm_clk_ctrl_config_regwen 20 20 100.00
clkmgr_csr_rw 1.120s 215.228us 20 20 100.00
prim_count_check 1 5 20.00
clkmgr_sec_cm 3.450s 1059.780us 1 5 20.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 50 50 100.00
clkmgr_regwen 6.410s 1235.828us 50 50 100.00
stress_all_with_rand_reset 49 50 98.00
clkmgr_stress_all_with_rand_reset 154.270s 64550.264us 49 50 98.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 23875984394096448756359881606461108245097458656795117705222868462142975406926 74
UVM_ERROR @ 1742367 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 1742367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 100017040801043778664922367987392910898461367822747734820012493983790291727299 74
UVM_ERROR @ 1661092 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 1661092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 111058309786493709773569995291925307917321192754517859870703820673060367042997 96
UVM_ERROR @ 56949890 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 56949890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 40926116720195417568235779889258898194973208226804832294607582741324706956767 108
UVM_ERROR @ 100684085 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 100684085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch
clkmgr_clk_handshake_intersig_mubi 76416720760121225238601438419983699137623522886617022633862625938079330367062 71
UVM_ERROR @ 5722186 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (0 [0x0] vs 9 [0x9]) extclk_status mismatch
UVM_INFO @ 5722186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(lc_clk_byp_req || (io_clk_byp_req_o != MuBi4False))'
clkmgr_stress_all_with_rand_reset 63214074828812253592311883206395407152559671394923603793312569545514873851582 102
Offending '(lc_clk_byp_req || (io_clk_byp_req_o != MuBi4False))'
UVM_ERROR @ 44481901 ps: (clkmgr_extclk_sva_if.sv:41) [ASSERT FAILED] IoClkBypReqFall_A
UVM_INFO @ 44481901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---