Simulation Results: edn

 
11/01/2026 00:07:26 sha: 8eebaba json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.32 %
  • code
  • 95.70 %
  • assert
  • 97.61 %
  • func
  • 92.66 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 93.96 %
  • toggle
  • 97.17 %
  • FSM
  • 91.94 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.330s 21.752us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.960s 55.006us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 0.880s 17.883us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 3.480s 178.969us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.350s 41.566us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.300s 79.645us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 0.880s 17.883us 20 20 100.00
edn_csr_aliasing 1.350s 41.566us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 86.220s 9168.636us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 86.220s 9168.636us 300 300 100.00
genbits 300 300 100.00
edn_genbits 86.220s 9168.636us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.450s 23.166us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.590s 55.989us 200 200 100.00
errs 100 100 100.00
edn_err 1.600s 307.029us 100 100 100.00
disable 100 100 100.00
edn_disable 1.210s 22.363us 50 50 100.00
edn_disable_auto_req_mode 1.430s 34.539us 50 50 100.00
stress_all 50 50 100.00
edn_stress_all 5.170s 382.046us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.940s 24.019us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.300s 38.741us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 2.920s 110.062us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 2.920s 110.062us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.960s 55.006us 5 5 100.00
edn_csr_rw 0.880s 17.883us 20 20 100.00
edn_csr_aliasing 1.350s 41.566us 5 5 100.00
edn_same_csr_outstanding 1.220s 118.650us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.960s 55.006us 5 5 100.00
edn_csr_rw 0.880s 17.883us 20 20 100.00
edn_csr_aliasing 1.350s 41.566us 5 5 100.00
edn_same_csr_outstanding 1.220s 118.650us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 2.040s 89.812us 20 20 100.00
edn_sec_cm 6.680s 1385.194us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.270s 15.392us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.590s 55.989us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 6.680s 1385.194us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 6.680s 1385.194us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 6.680s 1385.194us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 6.680s 1385.194us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.590s 55.989us 200 200 100.00
edn_sec_cm 6.680s 1385.194us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.590s 55.989us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 2.040s 89.812us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
edn_stress_all_with_rand_reset 89.940s 11289.234us 50 50 100.00

Error Messages

   Test seed line log context