Simulation Results: edn

 
11/01/2026 00:07:26 sha: 8eebaba json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.10 %
  • code
  • 95.71 %
  • assert
  • 97.14 %
  • func
  • 92.44 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.00 %
  • toggle
  • 96.15 %
  • FSM
  • 94.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
98.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.190s 39.721us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.990s 84.838us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.020s 16.177us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.260s 1045.105us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.520s 36.418us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.320s 55.949us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.020s 16.177us 20 20 100.00
edn_csr_aliasing 1.520s 36.418us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 6.050s 1133.738us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 6.050s 1133.738us 300 300 100.00
genbits 300 300 100.00
edn_genbits 6.050s 1133.738us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.090s 42.965us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.270s 124.218us 200 200 100.00
errs 100 100 100.00
edn_err 1.200s 24.958us 100 100 100.00
disable 100 100 100.00
edn_disable 1.110s 12.695us 50 50 100.00
edn_disable_auto_req_mode 1.270s 111.606us 50 50 100.00
stress_all 50 50 100.00
edn_stress_all 5.170s 426.248us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.070s 16.875us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.650s 124.579us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 2.820s 444.654us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 2.820s 444.654us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.990s 84.838us 5 5 100.00
edn_csr_rw 1.020s 16.177us 20 20 100.00
edn_csr_aliasing 1.520s 36.418us 5 5 100.00
edn_same_csr_outstanding 1.540s 146.196us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.990s 84.838us 5 5 100.00
edn_csr_rw 1.020s 16.177us 20 20 100.00
edn_csr_aliasing 1.520s 36.418us 5 5 100.00
edn_same_csr_outstanding 1.540s 146.196us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 7.210s 721.842us 20 20 100.00
edn_sec_cm 14.040s 1671.688us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 0.850s 50.990us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.270s 124.218us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 14.040s 1671.688us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 14.040s 1671.688us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 14.040s 1671.688us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 14.040s 1671.688us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.270s 124.218us 200 200 100.00
edn_sec_cm 14.040s 1671.688us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.270s 124.218us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 7.210s 721.842us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 49 50 98.00
edn_stress_all_with_rand_reset 73.880s 8394.812us 49 50 98.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1142) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
edn_stress_all_with_rand_reset 78117515121158830793403934037615026738360725102157111485032841953037800430323 178
UVM_ERROR @ 1413794738 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1413794738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---