flash_ctrl Simulation Results

Simulation Results: flash_ctrl

11/01/2026 00:07:26 sha: 8eebaba json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.92 %

code
95.78 %

assert
96.62 %

func
98.36 %

line
96.09 %

branch
97.45 %

cond
94.84 %

toggle
98.66 %

FSM
91.84 %

Validation stages

V1		100.00%
V2		99.30%
V2S		99.64%
V3		100.00%
unmapped		100.00%

145/145 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	flash_ctrl_smoke	134.900s	36.471us	50	50	100.00
smoke_hw				5	5	100.00
	flash_ctrl_smoke_hw	24.970s	55.246us	5	5	100.00
csr_hw_reset				5	5	100.00
	flash_ctrl_csr_hw_reset	38.420s	48.926us	5	5	100.00
csr_rw				20	20	100.00
	flash_ctrl_csr_rw	18.930s	58.356us	20	20	100.00
csr_bit_bash				5	5	100.00
	flash_ctrl_csr_bit_bash	69.810s	4428.877us	5	5	100.00
csr_aliasing				5	5	100.00
	flash_ctrl_csr_aliasing	68.360s	3064.009us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	flash_ctrl_csr_mem_rw_with_rand_reset	20.840s	86.181us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	flash_ctrl_csr_rw	18.930s	58.356us	20	20	100.00
	flash_ctrl_csr_aliasing	68.360s	3064.009us	5	5	100.00
mem_walk				5	5	100.00
	flash_ctrl_mem_walk	13.510s	119.415us	5	5	100.00
mem_partial_access				5	5	100.00
	flash_ctrl_mem_partial_access	13.750s	61.221us	5	5	100.00

1128/1136 passed

99.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sw_op				5	5	100.00
	flash_ctrl_sw_op	23.920s	21.853us	5	5	100.00
host_read_direct				5	5	100.00
	flash_ctrl_host_dir_rd	69.180s	55.692us	5	5	100.00
rma_hw_if				43	43	100.00
	flash_ctrl_hw_rma	1829.130s	1344400.763us	3	3	100.00
	flash_ctrl_hw_rma_reset	828.900s	170204.687us	20	20	100.00
	flash_ctrl_lcmgr_intg	13.700s	23.130us	20	20	100.00
host_controller_arb				5	5	100.00
	flash_ctrl_host_ctrl_arb	1839.800s	373433.372us	5	5	100.00
erase_suspend				5	5	100.00
	flash_ctrl_erase_suspend	412.640s	40890.530us	5	5	100.00
program_reset				30	30	100.00
	flash_ctrl_prog_reset	189.100s	12680.466us	30	30	100.00
full_memory_access				5	5	100.00
	flash_ctrl_full_mem_access	3357.310s	195652.168us	5	5	100.00
rd_buff_eviction				5	5	100.00
	flash_ctrl_rd_buff_evict	152.780s	1361.255us	5	5	100.00
rd_buff_eviction_w_ecc				98	100	98.00
	flash_ctrl_rw_evict	32.110s	74.823us	38	40	95.00
	flash_ctrl_rw_evict_all_en	31.870s	31.609us	40	40	100.00
	flash_ctrl_re_evict	36.310s	80.265us	20	20	100.00
host_arb				20	20	100.00
	flash_ctrl_phy_arb	245.000s	1517.354us	20	20	100.00
host_interleave				20	20	100.00
	flash_ctrl_phy_arb	245.000s	1517.354us	20	20	100.00
memory_protection				20	20	100.00
	flash_ctrl_mp_regions	887.430s	55417.453us	20	20	100.00
fetch_code				10	10	100.00
	flash_ctrl_fetch_code	29.190s	486.230us	10	10	100.00
all_partitions				20	20	100.00
	flash_ctrl_rand_ops	740.580s	482.477us	20	20	100.00
error_mp				9	10	90.00
	flash_ctrl_error_mp	596.000s	12959.810us	9	10	90.00
error_prog_win				10	10	100.00
	flash_ctrl_error_prog_win	560.480s	429.626us	10	10	100.00
error_prog_type				5	5	100.00
	flash_ctrl_error_prog_type	1349.950s	4943.721us	5	5	100.00
error_read_seed				20	20	100.00
	flash_ctrl_hw_read_seed_err	13.280s	23.353us	20	20	100.00
read_write_overflow				5	5	100.00
	flash_ctrl_oversize_error	196.460s	22682.398us	5	5	100.00
flash_ctrl_disable				50	50	100.00
	flash_ctrl_disable	22.520s	18.926us	50	50	100.00
flash_ctrl_connect				80	80	100.00
	flash_ctrl_connect	17.280s	86.666us	80	80	100.00
stress_all				5	5	100.00
	flash_ctrl_stress_all	767.660s	1471.866us	5	5	100.00
secret_partition				130	130	100.00
	flash_ctrl_hw_sec_otp	221.220s	50824.326us	50	50	100.00
	flash_ctrl_otp_reset	121.650s	40.515us	80	80	100.00
isolation_partition				3	3	100.00
	flash_ctrl_hw_rma	1829.130s	1344400.763us	3	3	100.00
interrupts				98	100	98.00
	flash_ctrl_intr_rd	190.220s	6060.477us	39	40	97.50
	flash_ctrl_intr_wr	88.200s	11464.847us	9	10	90.00
	flash_ctrl_intr_rd_slow_flash	327.990s	12349.759us	40	40	100.00
	flash_ctrl_intr_wr_slow_flash	334.520s	215898.419us	10	10	100.00
invalid_op				20	20	100.00
	flash_ctrl_invalid_op	78.640s	923.640us	20	20	100.00
mid_op_rst				5	5	100.00
	flash_ctrl_mid_op_rst	51.880s	2243.864us	5	5	100.00
double_bit_err				34	35	97.14
	flash_ctrl_read_word_sweep_derr	23.250s	25.213us	5	5	100.00
	flash_ctrl_ro_derr	143.970s	846.665us	10	10	100.00
	flash_ctrl_rw_derr	191.000s	2541.048us	10	10	100.00
	flash_ctrl_derr_detect	165.430s	4592.547us	5	5	100.00
	flash_ctrl_integrity	503.270s	16102.250us	4	5	80.00
single_bit_err				25	25	100.00
	flash_ctrl_read_word_sweep_serr	22.900s	61.973us	5	5	100.00
	flash_ctrl_ro_serr	126.790s	884.440us	10	10	100.00
	flash_ctrl_rw_serr	184.490s	8896.448us	10	10	100.00
singlebit_err_counter				5	5	100.00
	flash_ctrl_serr_counter	68.320s	1651.921us	5	5	100.00
singlebit_err_address				4	5	80.00
	flash_ctrl_serr_address	93.850s	1298.045us	4	5	80.00
scramble				61	62	98.39
	flash_ctrl_wo	198.350s	14525.003us	20	20	100.00
	flash_ctrl_write_word_sweep	15.060s	146.888us	1	1	100.00
	flash_ctrl_read_word_sweep	14.190s	28.101us	1	1	100.00
	flash_ctrl_ro	117.180s	2706.252us	20	20	100.00
	flash_ctrl_rw	497.220s	4762.576us	19	20	95.00
filesystem_support				5	5	100.00
	flash_ctrl_fs_sup	34.260s	569.780us	5	5	100.00
rma_write_process_error				23	23	100.00
	flash_ctrl_rma_err	1129.080s	443192.221us	3	3	100.00
	flash_ctrl_hw_prog_rma_wipe_err	261.410s	10016.908us	20	20	100.00
alert_test				50	50	100.00
	flash_ctrl_alert_test	14.950s	41.388us	50	50	100.00
intr_test				50	50	100.00
	flash_ctrl_intr_test	13.820s	30.559us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	flash_ctrl_tl_errors	18.920s	284.108us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	flash_ctrl_tl_errors	18.920s	284.108us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	flash_ctrl_csr_hw_reset	38.420s	48.926us	5	5	100.00
	flash_ctrl_csr_rw	18.930s	58.356us	20	20	100.00
	flash_ctrl_csr_aliasing	68.360s	3064.009us	5	5	100.00
	flash_ctrl_same_csr_outstanding	25.530s	122.115us	20	20	100.00
tl_d_partial_access				50	50	100.00
	flash_ctrl_csr_hw_reset	38.420s	48.926us	5	5	100.00
	flash_ctrl_csr_rw	18.930s	58.356us	20	20	100.00
	flash_ctrl_csr_aliasing	68.360s	3064.009us	5	5	100.00
	flash_ctrl_same_csr_outstanding	25.530s	122.115us	20	20	100.00

V2S

820/823 passed

99.64 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	85.890s	56.801us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	flash_ctrl_shadow_reg_errors	85.890s	56.801us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	85.890s	56.801us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	flash_ctrl_shadow_reg_errors	85.890s	56.801us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	flash_ctrl_shadow_reg_errors_with_csr_rw	70.920s	360.174us	20	20	100.00
tl_intg_err				25	25	100.00
	flash_ctrl_tl_intg_err	582.880s	1554.664us	20	20	100.00
	flash_ctrl_sec_cm	2192.960s	2286.368us	5	5	100.00
sec_cm_reg_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	582.880s	1554.664us	20	20	100.00
sec_cm_host_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	582.880s	1554.664us	20	20	100.00
sec_cm_mem_bus_integrity				6	6	100.00
	flash_ctrl_rd_intg	23.930s	244.881us	3	3	100.00
	flash_ctrl_wr_intg	14.740s	110.536us	3	3	100.00
sec_cm_scramble_key_sideload				50	50	100.00
	flash_ctrl_smoke	134.900s	36.471us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				260	260	100.00
	flash_ctrl_otp_reset	121.650s	40.515us	80	80	100.00
	flash_ctrl_disable	22.520s	18.926us	50	50	100.00
	flash_ctrl_sec_info_access	77.470s	8185.566us	50	50	100.00
	flash_ctrl_connect	17.280s	86.666us	80	80	100.00
sec_cm_ctrl_config_regwen				5	5	100.00
	flash_ctrl_config_regwen	13.070s	23.317us	5	5	100.00
sec_cm_data_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	18.930s	58.356us	20	20	100.00
sec_cm_data_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	85.890s	56.801us	20	20	100.00
sec_cm_info_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	18.930s	58.356us	20	20	100.00
sec_cm_info_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	85.890s	56.801us	20	20	100.00
sec_cm_bank_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	18.930s	58.356us	20	20	100.00
sec_cm_bank_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	85.890s	56.801us	20	20	100.00
sec_cm_mem_ctrl_global_esc				50	50	100.00
	flash_ctrl_disable	22.520s	18.926us	50	50	100.00
sec_cm_mem_ctrl_local_esc				6	6	100.00
	flash_ctrl_rd_intg	23.930s	244.881us	3	3	100.00
	flash_ctrl_access_after_disable	11.420s	20.960us	3	3	100.00
sec_cm_mem_addr_infection				3	3	100.00
	flash_ctrl_host_addr_infection	21.600s	71.278us	3	3	100.00
sec_cm_mem_disable_config_mubi				50	50	100.00
	flash_ctrl_disable	22.520s	18.926us	50	50	100.00
sec_cm_exec_config_redun				10	10	100.00
	flash_ctrl_fetch_code	29.190s	486.230us	10	10	100.00
sec_cm_mem_scramble				19	20	95.00
	flash_ctrl_rw	497.220s	4762.576us	19	20	95.00
sec_cm_mem_integrity				24	25	96.00
	flash_ctrl_rw_serr	184.490s	8896.448us	10	10	100.00
	flash_ctrl_rw_derr	191.000s	2541.048us	10	10	100.00
	flash_ctrl_integrity	503.270s	16102.250us	4	5	80.00
sec_cm_rma_entry_mem_sec_wipe				3	3	100.00
	flash_ctrl_hw_rma	1829.130s	1344400.763us	3	3	100.00
sec_cm_ctrl_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2192.960s	2286.368us	5	5	100.00
sec_cm_phy_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2192.960s	2286.368us	5	5	100.00
sec_cm_phy_prog_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2192.960s	2286.368us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2192.960s	2286.368us	5	5	100.00
sec_cm_phy_arbiter_ctrl_redun				5	5	100.00
	flash_ctrl_phy_arb_redun	18.890s	905.762us	5	5	100.00
sec_cm_phy_host_grant_ctrl_consistency				5	5	100.00
	flash_ctrl_phy_host_grant_err	11.500s	99.598us	5	5	100.00
sec_cm_phy_ack_ctrl_consistency				4	5	80.00
	flash_ctrl_phy_ack_consistency	12.970s	45.779us	4	5	80.00
sec_cm_fifo_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2192.960s	2286.368us	5	5	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2192.960s	2286.368us	5	5	100.00
sec_cm_prog_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2192.960s	2286.368us	5	5	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
asymmetric_read_path				1	1	100.00
	flash_ctrl_rd_ooo	36.490s	164.673us	1	1	100.00

unmapped

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				3	3	100.00
	flash_ctrl_basic_rw	620.370s	3603.216us	3	3	100.00

Error Messages

	Test	seed	line	log context
Job timed out after * minutes
	flash_ctrl_serr_address	11429375145014632251981000520139179994905629987592306297687635249065846977210	None	Job timed out after 60 minutes
	flash_ctrl_integrity	105711939935557684723032602410461409969944256568110235861884724265573713167753	None	Job timed out after 60 minutes
	flash_ctrl_intr_wr	86167831776394684671742608079740799635895032959770492195028431208959105522594	None	Job timed out after 60 minutes
	flash_ctrl_rw	67894829760714751215117099048820892240646715279550769014133004289425011035540	None	Job timed out after 60 minutes
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act () != exp ()
	flash_ctrl_phy_ack_consistency	27463027451236483817665020230464769045187120050650191788907135708471381987073	113	UVM_ERROR @ 17467.6 ns: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2a) != exp (0x26) UVM_INFO @ 17467.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_env_cfg.sv:714) [cfg] Check failed data[i] === exp_data[i] (* [] vs [*])
	flash_ctrl_error_mp	4936950406863518510799657788817063347944816311356238662495622663463145403295	261	UVM_ERROR @ 1539034.3 ns: (flash_ctrl_env_cfg.sv:714) [cfg] Check failed data[i] === exp_data[i] (0x689f4a0a [1101000100111110100101000001010] vs 0x297a63d4 [101001011110100110001111010100]) UVM_INFO @ 1539034.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value:
	flash_ctrl_rw_evict	72455797287933443961752146615237406571349883658899891828811308453587220805345	105	UVM_ERROR @ 74822.6 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0 UVM_INFO @ 74822.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp d3128d7a_5b436673:ffffffff_ffffffff mismatch!!
	flash_ctrl_intr_rd	36071774793874426345578154092089658251130519836179307492242690400841387205298	105	UVM_ERROR @ 1092437.0 ns: (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] 7: obs:exp d3128d7a_5b436673:ffffffff_ffffffff mismatch!! UVM_INFO @ 1092437.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.op_status.err reset value:
	flash_ctrl_rw_evict	68840241888666075003437459205450737726410344455003657441630284512801178065015	105	UVM_ERROR @ 39425.7 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0 UVM_INFO @ 39425.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---