Simulation Results: hmac

 
11/01/2026 00:07:26 sha: 8eebaba json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.98 %
  • code
  • 99.32 %
  • assert
  • 97.61 %
  • func
  • 100.00 %
  • line
  • 99.95 %
  • branch
  • 99.83 %
  • cond
  • 96.80 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 14.040s 880.682us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.230s 21.728us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.230s 19.813us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 12.980s 12026.331us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 7.360s 1843.444us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 809.610s 296660.977us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.230s 19.813us 20 20 100.00
hmac_csr_aliasing 7.360s 1843.444us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 85.810s 13178.013us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 78.180s 1851.714us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 278.770s 52813.611us 30 30 100.00
hmac_test_sha384_vectors 545.540s 25722.231us 75 75 100.00
hmac_test_sha512_vectors 526.540s 26939.680us 75 75 100.00
hmac_test_hmac256_vectors 15.370s 392.136us 50 50 100.00
hmac_test_hmac384_vectors 17.130s 1555.062us 60 60 100.00
hmac_test_hmac512_vectors 20.700s 400.596us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 39.540s 4260.859us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1077.400s 55630.614us 10 10 100.00
error 10 10 100.00
hmac_error 122.010s 10432.508us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 113.410s 12550.589us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 14.040s 880.682us 10 10 100.00
hmac_long_msg 85.810s 13178.013us 10 10 100.00
hmac_back_pressure 78.180s 1851.714us 25 25 100.00
hmac_datapath_stress 1077.400s 55630.614us 10 10 100.00
hmac_burst_wr 39.540s 4260.859us 50 50 100.00
hmac_stress_all 2710.960s 20354.356us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 14.040s 880.682us 10 10 100.00
hmac_long_msg 85.810s 13178.013us 10 10 100.00
hmac_back_pressure 78.180s 1851.714us 25 25 100.00
hmac_datapath_stress 1077.400s 55630.614us 10 10 100.00
hmac_wipe_secret 113.410s 12550.589us 10 10 100.00
hmac_test_sha256_vectors 278.770s 52813.611us 30 30 100.00
hmac_test_sha384_vectors 545.540s 25722.231us 75 75 100.00
hmac_test_sha512_vectors 526.540s 26939.680us 75 75 100.00
hmac_test_hmac256_vectors 15.370s 392.136us 50 50 100.00
hmac_test_hmac384_vectors 17.130s 1555.062us 60 60 100.00
hmac_test_hmac512_vectors 20.700s 400.596us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 14.040s 880.682us 10 10 100.00
hmac_long_msg 85.810s 13178.013us 10 10 100.00
hmac_back_pressure 78.180s 1851.714us 25 25 100.00
hmac_datapath_stress 1077.400s 55630.614us 10 10 100.00
hmac_burst_wr 39.540s 4260.859us 50 50 100.00
hmac_error 122.010s 10432.508us 10 10 100.00
hmac_wipe_secret 113.410s 12550.589us 10 10 100.00
hmac_test_sha256_vectors 278.770s 52813.611us 30 30 100.00
hmac_test_sha384_vectors 545.540s 25722.231us 75 75 100.00
hmac_test_sha512_vectors 526.540s 26939.680us 75 75 100.00
hmac_test_hmac256_vectors 15.370s 392.136us 50 50 100.00
hmac_test_hmac384_vectors 17.130s 1555.062us 60 60 100.00
hmac_test_hmac512_vectors 20.700s 400.596us 75 75 100.00
hmac_stress_all 2710.960s 20354.356us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2710.960s 20354.356us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.920s 18.760us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.950s 14.122us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 4.090s 72.270us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 4.090s 72.270us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.230s 21.728us 5 5 100.00
hmac_csr_rw 1.230s 19.813us 20 20 100.00
hmac_csr_aliasing 7.360s 1843.444us 5 5 100.00
hmac_same_csr_outstanding 2.880s 148.539us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.230s 21.728us 5 5 100.00
hmac_csr_rw 1.230s 19.813us 20 20 100.00
hmac_csr_aliasing 7.360s 1843.444us 5 5 100.00
hmac_same_csr_outstanding 2.880s 148.539us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_sec_cm 1.550s 267.435us 5 5 100.00
hmac_tl_intg_err 4.300s 294.932us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 4.300s 294.932us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 14.040s 880.682us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 7.780s 165.906us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 486.960s 5537.816us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.820s 67.965us 1 1 100.00

Error Messages

   Test seed line log context