Simulation Results: keymgr

 
11/01/2026 00:07:26 sha: 8eebaba json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.91 %
  • code
  • 98.86 %
  • assert
  • 97.72 %
  • func
  • 91.16 %
  • line
  • 99.13 %
  • branch
  • 99.01 %
  • cond
  • 97.87 %
  • toggle
  • 98.28 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.17%
V2S
99.42%
V3
58.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_smoke 24.930s 2572.510us 50 50 100.00
random 50 50 100.00
keymgr_random 60.490s 19570.859us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 1.270s 137.141us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 1.240s 15.663us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 21.590s 4440.253us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 10.110s 423.397us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 1.780s 55.875us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 1.240s 15.663us 20 20 100.00
keymgr_csr_aliasing 10.110s 423.397us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 72.770s 7560.562us 50 50 100.00
sideload 200 200 100.00
keymgr_sideload 33.360s 3137.830us 50 50 100.00
keymgr_sideload_kmac 25.870s 4174.315us 50 50 100.00
keymgr_sideload_aes 32.700s 1444.142us 50 50 100.00
keymgr_sideload_otbn 31.320s 2412.713us 50 50 100.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 20.580s 2897.347us 50 50 100.00
lc_disable 47 50 94.00
keymgr_lc_disable 6.180s 296.770us 47 50 94.00
kmac_error_response 49 50 98.00
keymgr_kmac_rsp_err 8.480s 376.897us 49 50 98.00
invalid_sw_input 50 50 100.00
keymgr_sw_invalid_input 57.740s 8647.474us 50 50 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 14.780s 667.657us 50 50 100.00
sync_async_fault_cross 50 50 100.00
keymgr_sync_async_fault_cross 12.030s 5427.134us 50 50 100.00
stress_all 47 50 94.00
keymgr_stress_all 233.530s 53392.533us 47 50 94.00
intr_test 50 50 100.00
keymgr_intr_test 1.020s 9.155us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.310s 43.357us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 3.260s 939.733us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 3.260s 939.733us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 1.270s 137.141us 5 5 100.00
keymgr_csr_rw 1.240s 15.663us 20 20 100.00
keymgr_csr_aliasing 10.110s 423.397us 5 5 100.00
keymgr_same_csr_outstanding 3.250s 2026.470us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 1.270s 137.141us 5 5 100.00
keymgr_csr_rw 1.240s 15.663us 20 20 100.00
keymgr_csr_aliasing 10.110s 423.397us 5 5 100.00
keymgr_same_csr_outstanding 3.250s 2026.470us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 11.480s 842.916us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_tl_intg_err 7.400s 1353.686us 20 20 100.00
keymgr_sec_cm 11.480s 842.916us 5 5 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 4.680s 257.747us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 4.680s 257.747us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 4.680s 257.747us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 4.680s 257.747us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 11.460s 504.487us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 11.480s 842.916us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 11.480s 842.916us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 7.400s 1353.686us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 4.680s 257.747us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 72.770s 7560.562us 50 50 100.00
sec_cm_reseed_config_regwen 70 70 100.00
keymgr_csr_rw 1.240s 15.663us 20 20 100.00
keymgr_random 60.490s 19570.859us 50 50 100.00
sec_cm_sw_binding_config_regwen 70 70 100.00
keymgr_csr_rw 1.240s 15.663us 20 20 100.00
keymgr_random 60.490s 19570.859us 50 50 100.00
sec_cm_max_key_ver_config_regwen 70 70 100.00
keymgr_csr_rw 1.240s 15.663us 20 20 100.00
keymgr_random 60.490s 19570.859us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 47 50 94.00
keymgr_lc_disable 6.180s 296.770us 47 50 94.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 14.780s 667.657us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 14.780s 667.657us 50 50 100.00
sec_cm_hw_key_sw_noaccess 50 50 100.00
keymgr_random 60.490s 19570.859us 50 50 100.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 13.770s 1202.720us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 11.480s 842.916us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 11.480s 842.916us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 11.480s 842.916us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 11.830s 1345.472us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 47 50 94.00
keymgr_lc_disable 6.180s 296.770us 47 50 94.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 11.480s 842.916us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 11.480s 842.916us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 11.480s 842.916us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 11.830s 1345.472us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 11.830s 1345.472us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 11.480s 842.916us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 11.830s 1345.472us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 11.480s 842.916us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 11.830s 1345.472us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 29 50 58.00
keymgr_stress_all_with_rand_reset 20.550s 1156.845us 29 50 58.00

Error Messages

   Test seed line log context
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share0_output_*
keymgr_stress_all 70735345310885879822990746134644671023911328673294380219316550065655997511454 4606
UVM_ERROR @ 7545098227 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (210860532 [0xc9179f4] vs 210860532 [0xc9179f4]) reg name: keymgr_reg_block.sw_share0_output_4
UVM_INFO @ 7545098227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_lc_disable 92752366931899795056857016043707863209207874690544485342887865163120842303577 245
UVM_ERROR @ 177300836 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_3
UVM_INFO @ 177300836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 89626577309746487062103122192857327619011626399803049495765826160501468845508 104
UVM_ERROR @ 1028772776 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1028772776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 80640798359176724904318438069593370061648190511684479306458455212273778471402 145
UVM_ERROR @ 252730642 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 252730642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 78153423936576288258601104103618735824752053483692465226556776051187306318363 599
UVM_ERROR @ 906365914 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 906365914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 42121037970083202661535370334159607652421458789905407811291692638916161978606 814
UVM_ERROR @ 441248880 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 441248880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 51632893391681468156614294404064118436239908947315183210384141686879100431973 265
UVM_ERROR @ 106679148 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 106679148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 50281878149067791888139205569578230106493139455964576523048605431811590085154 208
UVM_ERROR @ 232673703 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 232673703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 67357101450738195830297831008423587056750388321595199012372156133302008111111 254
UVM_ERROR @ 252961788 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 252961788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 107376689778030769249968671213684964435033890134268205466944466202330306007642 292
UVM_ERROR @ 403534486 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 403534486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 834388744426061461609637306450382636064823379567863405176268718729615466653 1432
UVM_ERROR @ 2383453186 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2383453186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 3728583995985259411102625857080885800425571459586351939533356356689703269159 171
UVM_ERROR @ 219356099 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 219356099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 104821213640643797621188828512465420809528982023513149525947163266027836903948 244
UVM_ERROR @ 130758378 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 130758378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 7256158409106450896103426143404759430894600185466383881848844983650266385249 411
UVM_ERROR @ 715611055 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 715611055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 42468501966454139974388209189086217323669773138260353855774933693045478709106 225
UVM_ERROR @ 537843040 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 537843040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 59091766449643316306949625679144587329474508885241815611907586223460537867495 530
UVM_ERROR @ 960999561 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10047 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 960999561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 90767280429457680632955165525690665752365583438113874874567444152792626069254 496
UVM_ERROR @ 1015833812 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1015833812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 65019712661398624358240364062285513441573330369869879010585567205437406596007 1003
UVM_ERROR @ 366465921 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 366465921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 23153760898270415129333199190470136480922158561396081713234394962271115309397 114
UVM_ERROR @ 1907440122 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1907440122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 69677546001870026710273876715467174106729504632033865440884018666564367678921 335
UVM_ERROR @ 961224983 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 961224983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 39456941346784343340602187701053624589386192230978043895652281139102874633616 408
UVM_ERROR @ 982861283 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 982861283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1142) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
keymgr_stress_all_with_rand_reset 11994863729888767177420097759220213165174975703027172974320559408822989136450 103
UVM_ERROR @ 677480726 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 677480726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*])
keymgr_stress_all_with_rand_reset 81154479756633448183061953565737436023169857640230684658032775714085244265288 1332
UVM_ERROR @ 1863317501 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
UVM_INFO @ 1863317501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_kmac_rsp_err 58286428532961185746960221626333002507797971743481560967719334520278620866845 518
UVM_ERROR @ 85305409 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 85305409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_lc_disable 21266547505403786383391580793121601410988471394548982598772281525392607605213 131
UVM_ERROR @ 43602320 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 43602320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StCreatorRootKey for Sealing Kmac
keymgr_stress_all 26881960750450769048944196438545554822716810497420323864489185833173296793025 289
UVM_ERROR @ 68509591 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (4375680721097930208462902432366422314847148622414296484045598986940019646487349456855593706957685936661557616664601375067322147864805506989817613480699636 [0x538be1c042b6dc60dc2f22e067e7284a41e85a6785e210c185389ad243c3fa66f4660e9192b1840204956e441197d33eac7ebbf3628fda79150be4590cb926f4] vs 4375680721097930208462902432366422314847148622414296484045598986940019646487349456855593706957685936661557616664601375067322147864805506989817613480699636 [0x538be1c042b6dc60dc2f22e067e7284a41e85a6785e210c185389ad243c3fa66f4660e9192b1840204956e441197d33eac7ebbf3628fda79150be4590cb926f4]) KMAC key at state StCreatorRootKey for Sealing Kmac
UVM_INFO @ 68509591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*])
keymgr_lc_disable 65158841572016972926535977104992305156672404774400780110009109830250123686194 270
UVM_ERROR @ 44369405 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (1 [0x1] vs 6 [0x6])
UVM_INFO @ 44369405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_*
keymgr_stress_all 11340347211368992855027365954357450679483925070004415582053800230295119870494 1464
UVM_ERROR @ 1410128162 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_1
UVM_INFO @ 1410128162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---