Simulation Results: kmac

 
11/01/2026 00:07:26 sha: 8eebaba json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.54 %
  • code
  • 94.07 %
  • assert
  • 97.83 %
  • func
  • 97.71 %
  • line
  • 99.27 %
  • branch
  • 97.15 %
  • cond
  • 94.45 %
  • toggle
  • 99.89 %
  • FSM
  • 79.58 %
Validation stages
V1
100.00%
V2
99.52%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 85.660s 15044.992us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.190s 63.883us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.310s 100.787us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 13.840s 4350.315us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 7.620s 537.408us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.120s 142.934us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.310s 100.787us 20 20 100.00
kmac_csr_aliasing 7.620s 537.408us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 0.850s 94.744us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.670s 42.769us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3980.690s 699685.236us 50 50 100.00
burst_write 49 50 98.00
kmac_burst_write 1384.950s 43216.214us 49 50 98.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2212.940s 774374.503us 5 5 100.00
kmac_test_vectors_sha3_256 1997.880s 122608.577us 5 5 100.00
kmac_test_vectors_sha3_384 1162.400s 19267.031us 5 5 100.00
kmac_test_vectors_sha3_512 1097.370s 47461.855us 5 5 100.00
kmac_test_vectors_shake_128 2629.410s 641191.100us 5 5 100.00
kmac_test_vectors_shake_256 1789.820s 317514.391us 5 5 100.00
kmac_test_vectors_kmac 3.990s 573.124us 5 5 100.00
kmac_test_vectors_kmac_xof 3.770s 164.247us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 505.100s 14977.745us 50 50 100.00
app 50 50 100.00
kmac_app 357.530s 25826.739us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 287.200s 8214.070us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 320.420s 17619.517us 50 50 100.00
error 50 50 100.00
kmac_error 507.190s 40690.393us 50 50 100.00
key_error 49 50 98.00
kmac_key_error 19.230s 12664.287us 49 50 98.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 9.110s 131.849us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 48.610s 4321.782us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 20.290s 1168.167us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 64.620s 25999.932us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 42.720s 868.182us 50 50 100.00
stress_all 48 50 96.00
kmac_stress_all 2613.530s 384974.399us 48 50 96.00
intr_test 50 50 100.00
kmac_intr_test 1.010s 41.101us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.220s 16.667us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 2.980s 155.071us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 2.980s 155.071us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.190s 63.883us 5 5 100.00
kmac_csr_rw 1.310s 100.787us 20 20 100.00
kmac_csr_aliasing 7.620s 537.408us 5 5 100.00
kmac_same_csr_outstanding 2.310s 277.483us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.190s 63.883us 5 5 100.00
kmac_csr_rw 1.310s 100.787us 20 20 100.00
kmac_csr_aliasing 7.620s 537.408us 5 5 100.00
kmac_same_csr_outstanding 2.310s 277.483us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.280s 129.039us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.280s 129.039us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.280s 129.039us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.280s 129.039us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 3.900s 801.833us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 4.170s 993.168us 20 20 100.00
kmac_sec_cm 126.730s 9133.557us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 4.170s 993.168us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 42.720s 868.182us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 85.660s 15044.992us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 505.100s 14977.745us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.280s 129.039us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 126.730s 9133.557us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 126.730s 9133.557us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 126.730s 9133.557us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 85.660s 15044.992us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 42.720s 868.182us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 126.730s 9133.557us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 317.760s 17734.395us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 85.660s 15044.992us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
kmac_stress_all_with_rand_reset 206.500s 4461.691us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
kmac_stress_all 66446596018561284957591185659037529932535890093400195904743925334986512780659 117
UVM_ERROR @ 4031342197 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 4031342197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 52955337942026097642506835908803762937356873507173765144666003097610053113292 169
UVM_ERROR @ 34348503785 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 34348503785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
kmac_burst_write 60132548879464971016736371830177108943686867293482317021087059244972300979219 246
UVM_FATAL @ 500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set!
kmac_key_error 74543497767891875044238054909934617711936116926950936245183144762238483626278 84
UVM_ERROR @ 1361654278 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
UVM_INFO @ 1361654278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---