Simulation Results: kmac

 
11/01/2026 00:07:26 sha: 8eebaba json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.43 %
  • code
  • 92.14 %
  • assert
  • 97.74 %
  • func
  • 96.40 %
  • line
  • 97.59 %
  • branch
  • 95.97 %
  • cond
  • 94.41 %
  • toggle
  • 100.00 %
  • FSM
  • 72.73 %
Validation stages
V1
100.00%
V2
98.57%
V2S
99.80%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 65.210s 31638.267us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 0.960s 66.465us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.030s 320.510us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 14.200s 2908.128us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 6.910s 2360.846us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.250s 1302.927us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.030s 320.510us 20 20 100.00
kmac_csr_aliasing 6.910s 2360.846us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 0.820s 17.125us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.440s 23.662us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3194.780s 185373.218us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1038.410s 278681.600us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 1954.540s 176950.376us 5 5 100.00
kmac_test_vectors_sha3_256 1753.300s 83613.756us 5 5 100.00
kmac_test_vectors_sha3_384 1346.630s 46723.295us 5 5 100.00
kmac_test_vectors_sha3_512 891.270s 41056.607us 5 5 100.00
kmac_test_vectors_shake_128 2271.800s 726978.597us 5 5 100.00
kmac_test_vectors_shake_256 1686.760s 222085.650us 5 5 100.00
kmac_test_vectors_kmac 3.140s 547.909us 5 5 100.00
kmac_test_vectors_kmac_xof 2.790s 96.452us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 389.510s 26392.442us 50 50 100.00
app 50 50 100.00
kmac_app 393.090s 227368.436us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 314.320s 76911.571us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 326.170s 15608.788us 50 50 100.00
error 50 50 100.00
kmac_error 389.260s 17613.659us 50 50 100.00
key_error 49 50 98.00
kmac_key_error 19.960s 20565.034us 49 50 98.00
sideload_invalid 39 50 78.00
kmac_sideload_invalid 123.160s 10034.875us 39 50 78.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 34.820s 1840.366us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 38.080s 3849.720us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 60.770s 6717.289us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 36.240s 1006.561us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2465.520s 159487.023us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 0.900s 52.719us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.190s 18.884us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 2.770s 321.562us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 2.770s 321.562us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 0.960s 66.465us 5 5 100.00
kmac_csr_rw 1.030s 320.510us 20 20 100.00
kmac_csr_aliasing 6.910s 2360.846us 5 5 100.00
kmac_same_csr_outstanding 2.150s 231.249us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 0.960s 66.465us 5 5 100.00
kmac_csr_rw 1.030s 320.510us 20 20 100.00
kmac_csr_aliasing 6.910s 2360.846us 5 5 100.00
kmac_same_csr_outstanding 2.150s 231.249us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 1.650s 93.885us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 1.650s 93.885us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 1.650s 93.885us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 1.650s 93.885us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
kmac_shadow_reg_errors_with_csr_rw 3.850s 786.212us 19 20 95.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 3.880s 525.337us 20 20 100.00
kmac_sec_cm 68.320s 5277.896us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 3.880s 525.337us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 36.240s 1006.561us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 65.210s 31638.267us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 389.510s 26392.442us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 1.650s 93.885us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 68.320s 5277.896us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 68.320s 5277.896us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 68.320s 5277.896us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 65.210s 31638.267us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 36.240s 1006.561us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 68.320s 5277.896us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 328.880s 19378.591us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 65.210s 31638.267us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
kmac_stress_all_with_rand_reset 294.380s 8105.505us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: *
kmac_shadow_reg_errors_with_csr_rw 83908968370710666413060877609965672811102268578931302308223000316627367587154 204
UVM_ERROR @ 56838852 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (569341009 [0x21ef7451] vs 1265518864 [0x4b6e4910]) Regname: kmac_reg_block.prefix_0.prefix_0 reset value: 0x0
UVM_INFO @ 56838852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10)
kmac_sideload_invalid 46654370818579530348571355718761427928410175821432106235749290559875627128688 84
UVM_FATAL @ 10141772422 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xba1e6000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10141772422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 27040872843674877036020969240563251904331925760003161877407167847964042545774 200
UVM_ERROR @ 2087837121 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2087837121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4)
kmac_sideload_invalid 113705768884461116641943192704151485950992215124172152711103980515239265250351 78
UVM_FATAL @ 10132225617 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb095f000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10132225617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13)
kmac_sideload_invalid 71738677340743207677073252575838606554857403878977252140804919932234680378235 88
UVM_FATAL @ 10053077728 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4fbfc000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10053077728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 98023245530549677458153542146569627480360055624183221637346688919292355372650 87
UVM_FATAL @ 10136552827 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6b30c000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
UVM_INFO @ 10136552827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
kmac_sideload_invalid 68040845581935422381005459151765626881454916201042936080317664415094936999528 75
UVM_FATAL @ 10033990980 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf1806000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10033990980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 76157209286901975991221198024768786088652115007745982306687702402157740865079 75
UVM_FATAL @ 10106902208 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb7133000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10106902208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.err_code reset value: *
kmac_key_error 23056580670065003335892463611608990708821493465995894720768419621934641619559 74
UVM_ERROR @ 49953900 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 16777216 [0x1000000]) Regname: kmac_reg_block.err_code reset value: 0x0
UVM_INFO @ 49953900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6)
kmac_sideload_invalid 80458959264183348657601011457697768740549020017868662537343716833058617730003 80
UVM_FATAL @ 10034875422 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4123000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10034875422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11)
kmac_sideload_invalid 105101448441840951113967184491403610200201542440485600407858369905192771483540 84
UVM_FATAL @ 10209275951 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x939a1000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10209275951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=40)
kmac_sideload_invalid 8343928567204314801519520494366987396188018112871498012950104712753309747312 120
UVM_FATAL @ 10454144040 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdec08000, Comparison=CompareOpEq, exp_data=0x1, call_count=40)
UVM_INFO @ 10454144040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
kmac_sideload_invalid 83762289868165285262258576357938972439191134610733932188989290674448450702010 76
UVM_FATAL @ 10021181572 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa5bc6000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10021181572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17)
kmac_sideload_invalid 47347694177842485498087498427561298044747865091119386649091400345460395888311 92
UVM_FATAL @ 10187778739 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5a23b000, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
UVM_INFO @ 10187778739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---