Simulation Results: otbn

 
11/01/2026 00:07:26 sha: 8eebaba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 98.00 %
  • code
  • 97.05 %
  • assert
  • 96.95 %
  • func
  • 100.00 %
  • block
  • 99.57 %
  • line
  • 99.66 %
  • branch
  • 94.93 %
  • toggle
  • 93.59 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.71%
V2S
99.47%
V3
20.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 16.000s 129.721us 1 1 100.00
single_binary 100 100 100.00
otbn_single 70.000s 289.283us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 9.000s 15.385us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 8.000s 15.585us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 10.000s 64.219us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 9.000s 18.004us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 12.000s 122.486us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 8.000s 15.585us 20 20 100.00
otbn_csr_aliasing 9.000s 18.004us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 39.000s 693.734us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 25.000s 253.811us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 34.000s 334.117us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 68.000s 266.284us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 317.000s 4221.533us 10 10 100.00
stress_all 9 10 90.00
otbn_stress_all 161.000s 2514.508us 9 10 90.00
lc_escalation 60 60 100.00
otbn_escalate 133.000s 554.107us 60 60 100.00
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 8.000s 31.764us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 20.000s 68.363us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 9.000s 89.753us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 9.000s 14.553us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 12.000s 271.373us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 12.000s 271.373us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 9.000s 15.385us 5 5 100.00
otbn_csr_rw 8.000s 15.585us 20 20 100.00
otbn_csr_aliasing 9.000s 18.004us 5 5 100.00
otbn_same_csr_outstanding 7.000s 26.878us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 9.000s 15.385us 5 5 100.00
otbn_csr_rw 8.000s 15.585us 20 20 100.00
otbn_csr_aliasing 9.000s 18.004us 5 5 100.00
otbn_same_csr_outstanding 7.000s 26.878us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 24 25 96.00
otbn_imem_err 16.000s 143.271us 10 10 100.00
otbn_dmem_err 19.000s 52.119us 14 15 93.33
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 20.000s 118.208us 5 5 100.00
otbn_controller_ispr_rdata_err 12.000s 76.412us 5 5 100.00
otbn_mac_bignum_acc_err 11.000s 73.878us 5 5 100.00
otbn_urnd_err 9.000s 30.377us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 6.000s 12.885us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 8.000s 20.222us 2 2 100.00
otbn_non_sec_partial_wipe 10 10 100.00
otbn_partial_wipe 9.000s 43.154us 10 10 100.00
tl_intg_err 25 25 100.00
otbn_tl_intg_err 57.000s 371.432us 20 20 100.00
otbn_sec_cm 232.000s 4225.052us 5 5 100.00
passthru_mem_tl_intg_err 18 20 90.00
otbn_passthru_mem_tl_intg_err 41.000s 216.653us 18 20 90.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 232.000s 4225.052us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 232.000s 4225.052us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 16.000s 129.721us 1 1 100.00
sec_cm_data_mem_integrity 14 15 93.33
otbn_dmem_err 19.000s 52.119us 14 15 93.33
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 16.000s 143.271us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 57.000s 371.432us 20 20 100.00
sec_cm_controller_fsm_global_esc 60 60 100.00
otbn_escalate 133.000s 554.107us 60 60 100.00
sec_cm_controller_fsm_local_esc 39 40 97.50
otbn_imem_err 16.000s 143.271us 10 10 100.00
otbn_dmem_err 19.000s 52.119us 14 15 93.33
otbn_zero_state_err_urnd 8.000s 31.764us 5 5 100.00
otbn_illegal_mem_acc 6.000s 12.885us 5 5 100.00
otbn_sec_cm 232.000s 4225.052us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 232.000s 4225.052us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 70.000s 289.283us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 16.000s 143.271us 10 10 100.00
otbn_dmem_err 19.000s 52.119us 14 15 93.33
otbn_zero_state_err_urnd 8.000s 31.764us 5 5 100.00
otbn_illegal_mem_acc 6.000s 12.885us 5 5 100.00
otbn_sec_cm 232.000s 4225.052us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 232.000s 4225.052us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 60 60 100.00
otbn_escalate 133.000s 554.107us 60 60 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 16.000s 143.271us 10 10 100.00
otbn_dmem_err 19.000s 52.119us 14 15 93.33
otbn_zero_state_err_urnd 8.000s 31.764us 5 5 100.00
otbn_illegal_mem_acc 6.000s 12.885us 5 5 100.00
otbn_sec_cm 232.000s 4225.052us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 232.000s 4225.052us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 70.000s 289.283us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 10.000s 31.103us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 7.000s 88.853us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 90.000s 771.193us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 90.000s 771.193us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 25.000s 95.196us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 232.000s 4225.052us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 232.000s 4225.052us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 16.000s 133.810us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 232.000s 4225.052us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 232.000s 4225.052us 5 5 100.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 20.000s 52.266us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 20.000s 52.266us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 20.000s 77.172us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 70.000s 289.283us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 70.000s 289.283us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 70.000s 289.283us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 317.000s 4221.533us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 70.000s 289.283us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 70.000s 289.283us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 11.000s 149.586us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 70.000s 289.283us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 232.000s 4225.052us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
otbn_stress_all_with_rand_reset 281.000s 1789.707us 2 10 20.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 11599184277422833268797684358873278941951241827484943474312033709986270426823 83
UVM_FATAL @ 2884190 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 2884190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 11907731809499627847971643019674917330218489452016481537551732483740171274157 512
UVM_FATAL @ 1789707033 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 1789707033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all 99691455575391461913321938010898147593542378461996425405488468109293285640843 171
UVM_FATAL @ 190949165 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 190949165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_dmem_err 51010039503280823284134810185567873380217260994650108458192752944284414910178 106
UVM_FATAL @ 20135393 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 20135393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 20560506228231696098167443228130090037630477328235775713017564963616905155706 98
UVM_FATAL @ 68765882 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 68765882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 11019102396482401991242616770222396037143806056759635693778707924232209550997 197
UVM_FATAL @ 143044661 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 143044661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 108945067406724031021775165314232861072541212059466281729897518571638551416815 255
UVM_FATAL @ 628399631 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 628399631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 113418402387806745959202813955695762762070761600324723713076926424591798093757 295
UVM_FATAL @ 2576211795 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 2576211795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 308289575343035510545323706314229622012532833232733651276431455590583314049 183
UVM_ERROR @ 253036773 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 253036773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 575093658317423256263137839053282484327359763476952842914446640520696595949 231
UVM_ERROR @ 307438525 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 307438525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 107382262774660901852815505702814661943513724564893270720702945960721726254603 175
UVM_ERROR @ 1350744238 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1350744238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 98081452772786123549714019693634788420690808008445672306527128047749019744041 179
UVM_ERROR @ 167862254 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 167862254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---