Simulation Results: rom_ctrl

 
11/01/2026 00:07:26 sha: 8eebaba json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.59 %
  • code
  • 99.55 %
  • assert
  • 96.94 %
  • func
  • 99.28 %
  • line
  • 99.46 %
  • branch
  • 99.64 %
  • cond
  • 98.66 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.02%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 4.370s 311.967us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 7.410s 165.535us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 6.870s 906.141us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 5.450s 129.403us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 5.170s 294.972us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.220s 178.852us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 6.870s 906.141us 20 20 100.00
rom_ctrl_csr_aliasing 5.170s 294.972us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 6.140s 1787.975us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 4.750s 555.995us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 5.900s 318.652us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 24.690s 614.892us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 7.090s 1822.229us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 6.550s 167.379us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 11.400s 543.142us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 11.400s 543.142us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 7.410s 165.535us 5 5 100.00
rom_ctrl_csr_rw 6.870s 906.141us 20 20 100.00
rom_ctrl_csr_aliasing 5.170s 294.972us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.290s 595.153us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 7.410s 165.535us 5 5 100.00
rom_ctrl_csr_rw 6.870s 906.141us 20 20 100.00
rom_ctrl_csr_aliasing 5.170s 294.972us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.290s 595.153us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 97.120s 8791.339us 17 20 85.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 28.890s 849.709us 20 20 100.00
tl_intg_err 21 25 84.00
rom_ctrl_sec_cm 227.760s 1362.498us 1 5 20.00
rom_ctrl_tl_intg_err 60.510s 315.382us 20 20 100.00
prim_fsm_check 1 5 20.00
rom_ctrl_sec_cm 227.760s 1362.498us 1 5 20.00
prim_count_check 1 5 20.00
rom_ctrl_sec_cm 227.760s 1362.498us 1 5 20.00
sec_cm_checker_ctr_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 97.120s 8791.339us 17 20 85.00
sec_cm_checker_ctrl_flow_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 97.120s 8791.339us 17 20 85.00
sec_cm_checker_fsm_local_esc 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 97.120s 8791.339us 17 20 85.00
sec_cm_compare_ctrl_flow_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 97.120s 8791.339us 17 20 85.00
sec_cm_compare_ctr_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 97.120s 8791.339us 17 20 85.00
sec_cm_compare_ctr_redun 1 5 20.00
rom_ctrl_sec_cm 227.760s 1362.498us 1 5 20.00
sec_cm_fsm_sparse 1 5 20.00
rom_ctrl_sec_cm 227.760s 1362.498us 1 5 20.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 4.370s 311.967us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 4.370s 311.967us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 4.370s 311.967us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 60.510s 315.382us 20 20 100.00
sec_cm_bus_local_esc 19 22 86.36
rom_ctrl_corrupt_sig_fatal_chk 97.120s 8791.339us 17 20 85.00
rom_ctrl_kmac_err_chk 7.090s 1822.229us 2 2 100.00
sec_cm_mux_mubi 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 97.120s 8791.339us 17 20 85.00
sec_cm_mux_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 97.120s 8791.339us 17 20 85.00
sec_cm_ctrl_redun 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 97.120s 8791.339us 17 20 85.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 28.890s 849.709us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 1 5 20.00
rom_ctrl_sec_cm 227.760s 1362.498us 1 5 20.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 537.420s 5803.637us 20 20 100.00

Error Messages

   Test seed line log context
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
rom_ctrl_sec_cm 32824586412645186770854446257653563572599688205934826474622469381511892813784 119
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 44531176ps failed at 44531176ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 44531176ps failed at 44531176ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 27634175922841178072926880567456425954068194824740359294677279970931717538337 166
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 6897349ps failed at 6897349ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 6897349ps failed at 6897349ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 4229859471081135812455155391107816135481893924213719573271360410365151361507 162
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 16977910ps failed at 16977910ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 16977910ps failed at 16977910ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 69588377913005430463968252483410765707508959261342890932466649103921689533900 84
UVM_ERROR @ 2235537776 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 2235537776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 68299072639205282048049357508881307550673467527314164144317773429729999583581 77
UVM_ERROR @ 462958053 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 462958053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 21141561421186319186981360592705986533517324951365253743066086992238899772535 85
UVM_ERROR @ 531999962 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 531999962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 44188052846343714197763385104520439652069701311158731073024637490933541359988 106
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respOpcode_A: started at 2188044ps failed at 2188044ps
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 2188044ps failed at 2188044ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'