rom_ctrl Simulation Results

Simulation Results: rom_ctrl

11/01/2026 00:07:26 sha: 8eebaba json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
98.48 %

code
99.36 %

assert
96.80 %

func
99.28 %

line
99.46 %

branch
99.27 %

cond
98.07 %

toggle
100.00 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		92.45%
V3		100.00%

92/92 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rom_ctrl_smoke	13.770s	4032.561us	2	2	100.00
csr_hw_reset				5	5	100.00
	rom_ctrl_csr_hw_reset	14.990s	1082.526us	5	5	100.00
csr_rw				20	20	100.00
	rom_ctrl_csr_rw	11.960s	297.525us	20	20	100.00
csr_bit_bash				5	5	100.00
	rom_ctrl_csr_bit_bash	11.200s	1038.493us	5	5	100.00
csr_aliasing				5	5	100.00
	rom_ctrl_csr_aliasing	10.320s	303.071us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	rom_ctrl_csr_mem_rw_with_rand_reset	10.480s	293.357us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	rom_ctrl_csr_rw	11.960s	297.525us	20	20	100.00
	rom_ctrl_csr_aliasing	10.320s	303.071us	5	5	100.00
mem_walk				5	5	100.00
	rom_ctrl_mem_walk	7.340s	294.477us	5	5	100.00
mem_partial_access				5	5	100.00
	rom_ctrl_mem_partial_access	9.370s	1485.779us	5	5	100.00

214/214 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_throughput_chk				2	2	100.00
	rom_ctrl_max_throughput_chk	8.760s	5155.466us	2	2	100.00
stress_all				20	20	100.00
	rom_ctrl_stress_all	53.690s	3127.195us	20	20	100.00
kmac_err_chk				2	2	100.00
	rom_ctrl_kmac_err_chk	19.990s	3581.133us	2	2	100.00
alert_test				50	50	100.00
	rom_ctrl_alert_test	12.110s	1065.085us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	rom_ctrl_tl_errors	14.220s	3699.417us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	rom_ctrl_tl_errors	14.220s	3699.417us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	rom_ctrl_csr_hw_reset	14.990s	1082.526us	5	5	100.00
	rom_ctrl_csr_rw	11.960s	297.525us	20	20	100.00
	rom_ctrl_csr_aliasing	10.320s	303.071us	5	5	100.00
	rom_ctrl_same_csr_outstanding	15.000s	2490.593us	20	20	100.00
tl_d_partial_access				50	50	100.00
	rom_ctrl_csr_hw_reset	14.990s	1082.526us	5	5	100.00
	rom_ctrl_csr_rw	11.960s	297.525us	20	20	100.00
	rom_ctrl_csr_aliasing	10.320s	303.071us	5	5	100.00
	rom_ctrl_same_csr_outstanding	15.000s	2490.593us	20	20	100.00

V2S

294/318 passed

92.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
corrupt_sig_fatal_chk				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	271.070s	6059.778us	20	20	100.00
passthru_mem_tl_intg_err				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	61.410s	24768.203us	20	20	100.00
tl_intg_err				21	25	84.00
	rom_ctrl_tl_intg_err	112.740s	1761.088us	20	20	100.00
	rom_ctrl_sec_cm	552.880s	1212.474us	1	5	20.00
prim_fsm_check				1	5	20.00
	rom_ctrl_sec_cm	552.880s	1212.474us	1	5	20.00
prim_count_check				1	5	20.00
	rom_ctrl_sec_cm	552.880s	1212.474us	1	5	20.00
sec_cm_checker_ctr_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	271.070s	6059.778us	20	20	100.00
sec_cm_checker_ctrl_flow_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	271.070s	6059.778us	20	20	100.00
sec_cm_checker_fsm_local_esc				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	271.070s	6059.778us	20	20	100.00
sec_cm_compare_ctrl_flow_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	271.070s	6059.778us	20	20	100.00
sec_cm_compare_ctr_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	271.070s	6059.778us	20	20	100.00
sec_cm_compare_ctr_redun				1	5	20.00
	rom_ctrl_sec_cm	552.880s	1212.474us	1	5	20.00
sec_cm_fsm_sparse				1	5	20.00
	rom_ctrl_sec_cm	552.880s	1212.474us	1	5	20.00
sec_cm_mem_scramble				2	2	100.00
	rom_ctrl_smoke	13.770s	4032.561us	2	2	100.00
sec_cm_mem_digest				2	2	100.00
	rom_ctrl_smoke	13.770s	4032.561us	2	2	100.00
sec_cm_intersig_mubi				2	2	100.00
	rom_ctrl_smoke	13.770s	4032.561us	2	2	100.00
sec_cm_bus_integrity				20	20	100.00
	rom_ctrl_tl_intg_err	112.740s	1761.088us	20	20	100.00
sec_cm_bus_local_esc				22	22	100.00
	rom_ctrl_corrupt_sig_fatal_chk	271.070s	6059.778us	20	20	100.00
	rom_ctrl_kmac_err_chk	19.990s	3581.133us	2	2	100.00
sec_cm_mux_mubi				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	271.070s	6059.778us	20	20	100.00
sec_cm_mux_consistency				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	271.070s	6059.778us	20	20	100.00
sec_cm_ctrl_redun				20	20	100.00
	rom_ctrl_corrupt_sig_fatal_chk	271.070s	6059.778us	20	20	100.00
sec_cm_ctrl_mem_integrity				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	61.410s	24768.203us	20	20	100.00
sec_cm_tlul_fifo_ctr_redun				1	5	20.00
	rom_ctrl_sec_cm	552.880s	1212.474us	1	5	20.00

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				20	20	100.00
	rom_ctrl_stress_all_with_rand_reset	480.270s	5801.468us	20	20	100.00

Error Messages

	Test	seed	line	log context
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
	rom_ctrl_sec_cm	30348804987695858006879899569729612487190266431396958670626510937250325414531	165	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 14739471ps failed at 14739471ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 14739471ps failed at 14739471ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	69059256287631643401876348553798956734347592680301061930823700698833629226678	418	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 80983056ps failed at 80983056ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 80983056ps failed at 80983056ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	65192709199596877222630660487323948935406769931837195878347525282104970787967	191	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 13895773ps failed at 13895773ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 13895773ps failed at 13895773ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	82028209747781402337119945220212172494849426671841252258037148776294493219901	289	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 16513954ps failed at 16513954ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 16513954ps failed at 16513954ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'