Simulation Results: rstmgr

 
11/01/2026 00:07:26 sha: 8eebaba json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.85 %
  • code
  • 99.66 %
  • assert
  • 98.13 %
  • func
  • 98.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 99.31 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
rstmgr_smoke 1.740s 192.745us 50 50 100.00
csr_hw_reset 5 5 100.00
rstmgr_csr_hw_reset 1.360s 120.824us 5 5 100.00
csr_rw 20 20 100.00
rstmgr_csr_rw 1.130s 79.916us 20 20 100.00
csr_bit_bash 5 5 100.00
rstmgr_csr_bit_bash 4.260s 1165.908us 5 5 100.00
csr_aliasing 5 5 100.00
rstmgr_csr_aliasing 2.580s 353.496us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rstmgr_csr_mem_rw_with_rand_reset 2.040s 188.031us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rstmgr_csr_rw 1.130s 79.916us 20 20 100.00
rstmgr_csr_aliasing 2.580s 353.496us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 50 50 100.00
rstmgr_por_stretcher 1.230s 186.029us 50 50 100.00
sw_rst 50 50 100.00
rstmgr_sw_rst 2.520s 529.784us 50 50 100.00
sw_rst_reset_race 50 50 100.00
rstmgr_sw_rst_reset_race 1.670s 251.154us 50 50 100.00
reset_info 50 50 100.00
rstmgr_reset 6.360s 1744.842us 50 50 100.00
cpu_info 50 50 100.00
rstmgr_reset 6.360s 1744.842us 50 50 100.00
alert_info 50 50 100.00
rstmgr_reset 6.360s 1744.842us 50 50 100.00
reset_info_capture 50 50 100.00
rstmgr_reset 6.360s 1744.842us 50 50 100.00
stress_all 50 50 100.00
rstmgr_stress_all 34.380s 12494.337us 50 50 100.00
alert_test 50 50 100.00
rstmgr_alert_test 1.190s 95.231us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rstmgr_tl_errors 3.080s 473.043us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rstmgr_tl_errors 3.080s 473.043us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rstmgr_csr_hw_reset 1.360s 120.824us 5 5 100.00
rstmgr_csr_rw 1.130s 79.916us 20 20 100.00
rstmgr_csr_aliasing 2.580s 353.496us 5 5 100.00
rstmgr_same_csr_outstanding 1.880s 264.116us 20 20 100.00
tl_d_partial_access 50 50 100.00
rstmgr_csr_hw_reset 1.360s 120.824us 5 5 100.00
rstmgr_csr_rw 1.130s 79.916us 20 20 100.00
rstmgr_csr_aliasing 2.580s 353.496us 5 5 100.00
rstmgr_same_csr_outstanding 1.880s 264.116us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rstmgr_tl_intg_err 3.250s 986.117us 20 20 100.00
rstmgr_sec_cm 26.490s 16798.633us 5 5 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 26.490s 16798.633us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 26.490s 16798.633us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
rstmgr_tl_intg_err 3.250s 986.117us 20 20 100.00
sec_cm_scan_intersig_mubi 50 50 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.650s 147.164us 50 50 100.00
sec_cm_leaf_rst_bkgn_chk 50 50 100.00
rstmgr_leaf_rst_cnsty 7.310s 2451.808us 50 50 100.00
sec_cm_leaf_rst_shadow 50 50 100.00
rstmgr_leaf_rst_shadow_attack 1.590s 301.622us 50 50 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 26.490s 16798.633us 5 5 100.00
sec_cm_sw_rst_config_regwen 20 20 100.00
rstmgr_csr_rw 1.130s 79.916us 20 20 100.00
sec_cm_dump_ctrl_config_regwen 20 20 100.00
rstmgr_csr_rw 1.130s 79.916us 20 20 100.00

Error Messages

   Test seed line log context