Simulation Results: spi_device

 
11/01/2026 00:07:26 sha: 8eebaba json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.97 %
  • code
  • 94.28 %
  • assert
  • 94.41 %
  • func
  • 99.21 %
  • line
  • 99.17 %
  • branch
  • 98.49 %
  • cond
  • 96.66 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
99.95%
V2S
100.00%
unmapped
98.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_device_flash_and_tpm 389.390s 254365.749us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_device_csr_hw_reset 1.440s 72.051us 5 5 100.00
csr_rw 20 20 100.00
spi_device_csr_rw 2.330s 1771.108us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_device_csr_bit_bash 24.980s 7566.668us 5 5 100.00
csr_aliasing 5 5 100.00
spi_device_csr_aliasing 14.500s 629.023us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_device_csr_mem_rw_with_rand_reset 3.420s 317.106us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_device_csr_rw 2.330s 1771.108us 20 20 100.00
spi_device_csr_aliasing 14.500s 629.023us 5 5 100.00
mem_walk 5 5 100.00
spi_device_mem_walk 0.830s 16.983us 5 5 100.00
mem_partial_access 5 5 100.00
spi_device_mem_partial_access 1.730s 76.769us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 50 50 100.00
spi_device_csb_read 1.190s 89.045us 50 50 100.00
mem_parity 20 20 100.00
spi_device_mem_parity 1.440s 38.421us 20 20 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.730s 19.050us 1 1 100.00
tpm_read 50 50 100.00
spi_device_tpm_rw 8.740s 297.456us 50 50 100.00
tpm_write 50 50 100.00
spi_device_tpm_rw 8.740s 297.456us 50 50 100.00
tpm_hw_reg 100 100 100.00
spi_device_tpm_read_hw_reg 36.570s 71845.294us 50 50 100.00
spi_device_tpm_sts_read 1.350s 75.465us 50 50 100.00
tpm_fully_random_case 50 50 100.00
spi_device_tpm_all 43.870s 38123.240us 50 50 100.00
pass_cmd_filtering 100 100 100.00
spi_device_pass_cmd_filtering 28.110s 29747.552us 50 50 100.00
spi_device_flash_all 349.310s 79731.907us 50 50 100.00
pass_addr_translation 100 100 100.00
spi_device_pass_addr_payload_swap 30.130s 28993.234us 50 50 100.00
spi_device_flash_all 349.310s 79731.907us 50 50 100.00
pass_payload_translation 100 100 100.00
spi_device_pass_addr_payload_swap 30.130s 28993.234us 50 50 100.00
spi_device_flash_all 349.310s 79731.907us 50 50 100.00
cmd_info_slots 50 50 100.00
spi_device_flash_all 349.310s 79731.907us 50 50 100.00
cmd_read_status 100 100 100.00
spi_device_intercept 23.240s 14701.589us 50 50 100.00
spi_device_flash_all 349.310s 79731.907us 50 50 100.00
cmd_read_jedec 100 100 100.00
spi_device_intercept 23.240s 14701.589us 50 50 100.00
spi_device_flash_all 349.310s 79731.907us 50 50 100.00
cmd_read_sfdp 100 100 100.00
spi_device_intercept 23.240s 14701.589us 50 50 100.00
spi_device_flash_all 349.310s 79731.907us 50 50 100.00
cmd_fast_read 100 100 100.00
spi_device_intercept 23.240s 14701.589us 50 50 100.00
spi_device_flash_all 349.310s 79731.907us 50 50 100.00
cmd_read_pipeline 100 100 100.00
spi_device_intercept 23.240s 14701.589us 50 50 100.00
spi_device_flash_all 349.310s 79731.907us 50 50 100.00
flash_cmd_upload 50 50 100.00
spi_device_upload 22.980s 52251.287us 50 50 100.00
mailbox_command 50 50 100.00
spi_device_mailbox 115.150s 14867.939us 50 50 100.00
mailbox_cross_outside_command 50 50 100.00
spi_device_mailbox 115.150s 14867.939us 50 50 100.00
mailbox_cross_inside_command 50 50 100.00
spi_device_mailbox 115.150s 14867.939us 50 50 100.00
cmd_read_buffer 100 100 100.00
spi_device_flash_mode 35.570s 17818.236us 50 50 100.00
spi_device_read_buffer_direct 16.880s 3106.459us 50 50 100.00
cmd_dummy_cycle 100 100 100.00
spi_device_mailbox 115.150s 14867.939us 50 50 100.00
spi_device_flash_all 349.310s 79731.907us 50 50 100.00
quad_spi 50 50 100.00
spi_device_flash_all 349.310s 79731.907us 50 50 100.00
dual_spi 50 50 100.00
spi_device_flash_all 349.310s 79731.907us 50 50 100.00
4b_3b_feature 50 50 100.00
spi_device_cfg_cmd 36.270s 14650.328us 50 50 100.00
write_enable_disable 50 50 100.00
spi_device_cfg_cmd 36.270s 14650.328us 50 50 100.00
TPM_with_flash_or_passthrough_mode 50 50 100.00
spi_device_flash_and_tpm 389.390s 254365.749us 50 50 100.00
tpm_and_flash_trans_with_min_inactive_time 50 50 100.00
spi_device_flash_and_tpm_min_idle 440.160s 81316.867us 50 50 100.00
stress_all 49 50 98.00
spi_device_stress_all 1096.650s 2310616.121us 49 50 98.00
alert_test 50 50 100.00
spi_device_alert_test 1.140s 15.061us 50 50 100.00
intr_test 50 50 100.00
spi_device_intr_test 1.010s 39.983us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_device_tl_errors 4.240s 874.457us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_device_tl_errors 4.240s 874.457us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_device_csr_hw_reset 1.440s 72.051us 5 5 100.00
spi_device_csr_rw 2.330s 1771.108us 20 20 100.00
spi_device_csr_aliasing 14.500s 629.023us 5 5 100.00
spi_device_same_csr_outstanding 3.550s 1002.526us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_device_csr_hw_reset 1.440s 72.051us 5 5 100.00
spi_device_csr_rw 2.330s 1771.108us 20 20 100.00
spi_device_csr_aliasing 14.500s 629.023us 5 5 100.00
spi_device_same_csr_outstanding 3.550s 1002.526us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_device_tl_intg_err 17.740s 4352.259us 20 20 100.00
spi_device_sec_cm 1.480s 1481.637us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
spi_device_tl_intg_err 17.740s 4352.259us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 49 50 98.00
spi_device_flash_mode_ignore_cmds 1167.720s 1500000.000us 49 50 98.00

Error Messages

   Test seed line log context
UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp *
spi_device_stress_all 57074872928986128497181242266089734817298807254668581480182830062297788944843 93
UVM_ERROR @ 1154273949 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (14011392 [0xd5cc00] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0xd5cc00 != exp 0x0
UVM_INFO @ 1637230930 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 0/9
UVM_INFO @ 1637230930 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 1/9
UVM_INFO @ 3082488244 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/7
UVM_INFO @ 3598550258 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 1/9
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_device_flash_mode_ignore_cmds 106359335073608337847243628906440560520991902802503708624315009339117945309461 117
UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---