Simulation Results: sram_ctrl

 
11/01/2026 00:07:26 sha: 8eebaba json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.77 %
  • code
  • 96.15 %
  • assert
  • 95.83 %
  • func
  • 98.33 %
  • line
  • 99.11 %
  • branch
  • 98.02 %
  • cond
  • 92.90 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.59%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 95.200s 5089.266us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.070s 29.518us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.060s 14.831us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.630s 470.347us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.090s 77.097us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 6.180s 1352.495us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.060s 14.831us 20 20 100.00
sram_ctrl_csr_aliasing 1.090s 77.097us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 335.700s 114850.641us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 178.010s 20948.596us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1695.600s 35996.323us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 390.070s 6318.866us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 2377.970s 221237.944us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1348.900s 19812.873us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 149.220s 94351.712us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1509.600s 32003.699us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 86.130s 868.956us 50 50 100.00
sram_ctrl_partial_access_b2b 586.470s 128452.302us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 96.130s 768.469us 50 50 100.00
sram_ctrl_throughput_w_partial_write 97.920s 3119.945us 50 50 100.00
sram_ctrl_throughput_w_readback 112.350s 3665.037us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1500.660s 39360.331us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 6.480s 4781.498us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 9956.410s 1012560.006us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.070s 43.911us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 5.420s 571.940us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 5.420s 571.940us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.070s 29.518us 5 5 100.00
sram_ctrl_csr_rw 1.060s 14.831us 20 20 100.00
sram_ctrl_csr_aliasing 1.090s 77.097us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.240s 37.422us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.070s 29.518us 5 5 100.00
sram_ctrl_csr_rw 1.060s 14.831us 20 20 100.00
sram_ctrl_csr_aliasing 1.090s 77.097us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.240s 37.422us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 66.360s 14211.543us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_sec_cm 1.170s 31.448us 0 5 0.00
sram_ctrl_tl_intg_err 3.100s 1187.014us 20 20 100.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 1.170s 31.448us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 3.100s 1187.014us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1500.660s 39360.331us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1500.660s 39360.331us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.060s 14.831us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1509.600s 32003.699us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1509.600s 32003.699us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1509.600s 32003.699us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 149.220s 94351.712us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 47 50 94.00
sram_ctrl_mubi_enc_err 8.840s 3730.945us 47 50 94.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 66.360s 14211.543us 20 20 100.00
sec_cm_mem_readback 33 50 66.00
sram_ctrl_readback_err 11.070s 7387.663us 33 50 66.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 95.200s 5089.266us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 95.200s 5089.266us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1509.600s 32003.699us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 1.170s 31.448us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 149.220s 94351.712us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 1.170s 31.448us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.170s 31.448us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 95.200s 5089.266us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.170s 31.448us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 137.530s 5743.968us 50 50 100.00

Error Messages

   Test seed line log context
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
sram_ctrl_sec_cm 58453782805607795930479223712368518484619900588301359612883774217271569755934 99
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 12382956ps failed at 12382956ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respOpcode_A: started at 12393482ps failed at 12393482ps
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 34302205010185403260527972795975204860306185140341588252008255287470111968565 96
UVM_ERROR @ 12373159 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 12373159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 34662802975255797277632595574269983133629976568219086527214355892136908852677 96
UVM_ERROR @ 2372257 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 2372257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 4103545402035225286548051753888431786396219012580846370903647987014915311463 96
UVM_ERROR @ 4215571 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 4215571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 43913458517609927818772442609044418808294629395830379000498143146708879612588 95
UVM_ERROR @ 2740305062 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4d) != exp (0x40)
UVM_INFO @ 2740305062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 2135177147073940744342198714831006274951385867632080358350333690139927623972 95
UVM_ERROR @ 1371554810 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x34) != exp (0x6a)
UVM_INFO @ 1371554810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 115650129114061435233208554282881727114886508176754800753586590519932371900141 95
UVM_ERROR @ 4130489203 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2e) != exp (0x61)
UVM_INFO @ 4130489203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 102925428361739957552289829079630081437877863210739682575257743641131878561665 95
UVM_ERROR @ 658701348 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xc) != exp (0x5e)
UVM_INFO @ 658701348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 32887784015465765902276025237199996244752100970816448788776415334400334497053 95
UVM_ERROR @ 5056657632 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x11) != exp (0x53)
UVM_INFO @ 5056657632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 44085148131019582004023117419644466511475860807509112940273375689445896159698 95
UVM_ERROR @ 2544214372 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x61) != exp (0x75)
UVM_INFO @ 2544214372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 95218401033792308236182475357113828050437508000683083549758216288768322233214 95
UVM_ERROR @ 842924761 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x13) != exp (0x53)
UVM_INFO @ 842924761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 60032315255301888493000072398163929655331871654714368455085548899465587375944 95
UVM_ERROR @ 2796185367 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x4c) != exp (0x1c)
UVM_INFO @ 2796185367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 71065610333870168629481683906143763478642176847815821996948721349264380426284 95
UVM_ERROR @ 1369198820 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x33) != exp (0x1e)
UVM_INFO @ 1369198820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 58896524917832600634756754568190830940299377865497654812685121289568994966224 95
UVM_ERROR @ 2445379898 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x49) != exp (0x66)
UVM_INFO @ 2445379898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 36331225160737456557006853667141406677022427308802737005291242820119438435920 95
UVM_ERROR @ 659698036 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5c) != exp (0x61)
UVM_INFO @ 659698036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 113774472883315582959207396375060384614034147384024947615401480468842417338935 95
UVM_ERROR @ 1342416721 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7) != exp (0x51)
UVM_INFO @ 1342416721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 57129560544158796198479900808326058541495613895116418412580838757553922258839 95
UVM_ERROR @ 2435084167 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x74) != exp (0x75)
UVM_INFO @ 2435084167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 85355286110594199168474416173260086146597743963740063719752245988231116854921 95
UVM_ERROR @ 6577762797 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x24) != exp (0x46)
UVM_INFO @ 6577762797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 19251008023874523651606804553024737396022289000928345623144897107810982649213 95
UVM_ERROR @ 1432297852 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x14) != exp (0x63)
UVM_INFO @ 1432297852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 50647198578757653405618070185741754582369657399372789002652063535446508040965 95
UVM_ERROR @ 1412489670 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x17) != exp (0x5c)
UVM_INFO @ 1412489670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 19635824562269208461075379280437846713407836395635611023381765487304850433873 95
UVM_ERROR @ 4381071709 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7d) != exp (0x63)
UVM_INFO @ 4381071709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 37825469929799982912924448422361671756006131037313014136385587294147681213639 100
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 31448300 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 31448300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 16964684410347987124722735912438165678611477425683100280723538141451199188035 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2769862147 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2769862147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 36058653471084632440201278721112111931232817999664392981835283612120844965384 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2749750101 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2749750101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 46753103587316286731733467607480835053756972294114021657552076402274710324126 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2568827345 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2568827345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---