sram_ctrl Simulation Results

Simulation Results: sram_ctrl

11/01/2026 00:07:26 sha: 8eebaba json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.75 %

code
96.12 %

assert
95.79 %

func
98.33 %

line
99.07 %

branch
97.98 %

cond
92.90 %

toggle
90.66 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		94.36%
V3		96.00%

230/230 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	sram_ctrl_smoke	90.980s	2122.149us	50	50	100.00
csr_hw_reset				5	5	100.00
	sram_ctrl_csr_hw_reset	1.030s	51.993us	5	5	100.00
csr_rw				20	20	100.00
	sram_ctrl_csr_rw	1.050s	16.853us	20	20	100.00
csr_bit_bash				5	5	100.00
	sram_ctrl_csr_bit_bash	1.880s	467.275us	5	5	100.00
csr_aliasing				5	5	100.00
	sram_ctrl_csr_aliasing	1.010s	47.684us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	sram_ctrl_csr_mem_rw_with_rand_reset	3.050s	164.873us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	sram_ctrl_csr_rw	1.050s	16.853us	20	20	100.00
	sram_ctrl_csr_aliasing	1.010s	47.684us	5	5	100.00
mem_walk				50	50	100.00
	sram_ctrl_mem_walk	13.240s	2284.444us	50	50	100.00
mem_partial_access				50	50	100.00
	sram_ctrl_mem_partial_access	7.860s	1767.498us	50	50	100.00

890/890 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
multiple_keys				50	50	100.00
	sram_ctrl_multiple_keys	1163.270s	32081.744us	50	50	100.00
stress_pipeline				50	50	100.00
	sram_ctrl_stress_pipeline	388.980s	17362.906us	50	50	100.00
bijection				50	50	100.00
	sram_ctrl_bijection	87.370s	13263.040us	50	50	100.00
access_during_key_req				50	50	100.00
	sram_ctrl_access_during_key_req	1182.690s	7613.252us	50	50	100.00
lc_escalation				50	50	100.00
	sram_ctrl_lc_escalation	15.830s	11418.093us	50	50	100.00
executable				50	50	100.00
	sram_ctrl_executable	1137.210s	18912.554us	50	50	100.00
partial_access				100	100	100.00
	sram_ctrl_partial_access	94.260s	812.593us	50	50	100.00
	sram_ctrl_partial_access_b2b	525.510s	133007.284us	50	50	100.00
max_throughput				150	150	100.00
	sram_ctrl_max_throughput	91.580s	261.780us	50	50	100.00
	sram_ctrl_throughput_w_partial_write	103.320s	664.988us	50	50	100.00
	sram_ctrl_throughput_w_readback	101.800s	1041.063us	50	50	100.00
regwen				50	50	100.00
	sram_ctrl_regwen	1470.910s	77343.602us	50	50	100.00
ram_cfg				50	50	100.00
	sram_ctrl_ram_cfg	1.320s	72.394us	50	50	100.00
stress_all				50	50	100.00
	sram_ctrl_stress_all	4292.930s	29941.171us	50	50	100.00
alert_test				50	50	100.00
	sram_ctrl_alert_test	1.030s	26.863us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	sram_ctrl_tl_errors	4.900s	132.812us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	sram_ctrl_tl_errors	4.900s	132.812us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	sram_ctrl_csr_hw_reset	1.030s	51.993us	5	5	100.00
	sram_ctrl_csr_rw	1.050s	16.853us	20	20	100.00
	sram_ctrl_csr_aliasing	1.010s	47.684us	5	5	100.00
	sram_ctrl_same_csr_outstanding	1.070s	20.179us	20	20	100.00
tl_d_partial_access				50	50	100.00
	sram_ctrl_csr_hw_reset	1.030s	51.993us	5	5	100.00
	sram_ctrl_csr_rw	1.050s	16.853us	20	20	100.00
	sram_ctrl_csr_aliasing	1.010s	47.684us	5	5	100.00
	sram_ctrl_same_csr_outstanding	1.070s	20.179us	20	20	100.00

V2S

736/780 passed

94.36 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
passthru_mem_tl_intg_err				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	4.730s	1116.515us	20	20	100.00
tl_intg_err				19	25	76.00
	sram_ctrl_sec_cm	0.980s	3.882us	0	5	0.00
	sram_ctrl_tl_intg_err	4.140s	832.463us	19	20	95.00
prim_count_check				0	5	0.00
	sram_ctrl_sec_cm	0.980s	3.882us	0	5	0.00
sec_cm_bus_integrity				19	20	95.00
	sram_ctrl_tl_intg_err	4.140s	832.463us	19	20	95.00
sec_cm_ctrl_config_regwen				50	50	100.00
	sram_ctrl_regwen	1470.910s	77343.602us	50	50	100.00
sec_cm_readback_config_regwen				50	50	100.00
	sram_ctrl_regwen	1470.910s	77343.602us	50	50	100.00
sec_cm_exec_config_regwen				20	20	100.00
	sram_ctrl_csr_rw	1.050s	16.853us	20	20	100.00
sec_cm_exec_config_mubi				50	50	100.00
	sram_ctrl_executable	1137.210s	18912.554us	50	50	100.00
sec_cm_exec_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1137.210s	18912.554us	50	50	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1137.210s	18912.554us	50	50	100.00
sec_cm_lc_escalate_en_intersig_mubi				50	50	100.00
	sram_ctrl_lc_escalation	15.830s	11418.093us	50	50	100.00
sec_cm_prim_ram_ctrl_mubi				46	50	92.00
	sram_ctrl_mubi_enc_err	1.530s	40.118us	46	50	92.00
sec_cm_mem_integrity				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	4.730s	1116.515us	20	20	100.00
sec_cm_mem_readback				42	50	84.00
	sram_ctrl_readback_err	1.530s	466.035us	42	50	84.00
sec_cm_mem_scramble				50	50	100.00
	sram_ctrl_smoke	90.980s	2122.149us	50	50	100.00
sec_cm_addr_scramble				50	50	100.00
	sram_ctrl_smoke	90.980s	2122.149us	50	50	100.00
sec_cm_instr_bus_lc_gated				50	50	100.00
	sram_ctrl_executable	1137.210s	18912.554us	50	50	100.00
sec_cm_ram_tl_lc_gate_fsm_sparse				0	5	0.00
	sram_ctrl_sec_cm	0.980s	3.882us	0	5	0.00
sec_cm_key_global_esc				50	50	100.00
	sram_ctrl_lc_escalation	15.830s	11418.093us	50	50	100.00
sec_cm_key_local_esc				0	5	0.00
	sram_ctrl_sec_cm	0.980s	3.882us	0	5	0.00
sec_cm_init_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	0.980s	3.882us	0	5	0.00
sec_cm_scramble_key_sideload				50	50	100.00
	sram_ctrl_smoke	90.980s	2122.149us	50	50	100.00
sec_cm_tlul_fifo_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	0.980s	3.882us	0	5	0.00

48/50 passed

96.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				48	50	96.00
	sram_ctrl_stress_all_with_rand_reset	799.720s	3465.478us	48	50	96.00

Error Messages

	Test	seed	line	log context
Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	sram_ctrl_sec_cm	47377957676355735192482760976644337689065151846866912032194887336426976464806	98	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' UVM_ERROR @ 6453687 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 6453687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act () != exp ()
	sram_ctrl_readback_err	52618664487186505941164505355703617807952297344920391998091865087991375497398	95	UVM_ERROR @ 466034811 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2) != exp (0x11) UVM_INFO @ 466034811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	54710809346565795689192312419918355397451621732935138534383101287371426850768	95	UVM_ERROR @ 31991456 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x30) != exp (0x18) UVM_INFO @ 31991456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	98548470970243574413676374072513119659872391745443926383128530111538818922093	95	UVM_ERROR @ 33193160 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x52) != exp (0x19) UVM_INFO @ 33193160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	45480097634949544464952396605019826305131551866574152978295282310312090770061	95	UVM_ERROR @ 87914701 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6f) != exp (0x5d) UVM_INFO @ 87914701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	21007835937404026933673211510033022707118228815569739908034236872876548934406	95	UVM_ERROR @ 45928051 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x54) != exp (0x6) UVM_INFO @ 45928051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	76466477768905510132282745749424513877314321098447269859713700069476010357583	95	UVM_ERROR @ 104141130 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3f) != exp (0x73) UVM_INFO @ 104141130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	28829983434393126677756280508474700305094517832416410111659373467841408315225	95	UVM_ERROR @ 49372939 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x29) != exp (0x4e) UVM_INFO @ 49372939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	107728778829273517329040931106235773959033809823314034751876228241655286554740	95	UVM_ERROR @ 45252836 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xf) != exp (0x71) UVM_INFO @ 45252836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
	sram_ctrl_sec_cm	31950567599551488605249621355747452291199395052572306355751294158811525143143	96	Offending '(!$isunknown(rdata_o))' UVM_ERROR @ 3763683 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A UVM_INFO @ 3763683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.status.init_error reset value:
	sram_ctrl_sec_cm	93861659555094359014039686829696239087761172013323278257492565427220616324967	96	UVM_ERROR @ 4606017 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 4606017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	73124573699715975657845996318347465656141112570863561245865119033210599962441	96	UVM_ERROR @ 3882313 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 3882313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	3018604592624605024756563981125351449789533945360890673491155261913015621619	97	UVM_ERROR @ 6315058 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 6315058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
	sram_ctrl_mubi_enc_err	1716256563712571143191391745496542477324757854371592949761688213998056359788	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 326339328 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 326339328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	20862737806235467460871657480063884790769871596926065502717348616894068023884	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 49439747 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 49439747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	105016401752348184828709425087978955691891729405247149020309531543763486166084	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 66828891 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 66828891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	26252031101059939746963305836662444886756484131797923476470778649584426749013	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 36521927 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 36521927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	sram_ctrl_stress_all_with_rand_reset	56103518383477231216396788210337789605226546464892676208504003609288561885919	215	UVM_ERROR @ 3130099920 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 3130099920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1142) [sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
	sram_ctrl_stress_all_with_rand_reset	21265177271961720676705972325641942530620005724160242227646158630381545732813	426	UVM_ERROR @ 5532871489 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. UVM_INFO @ 5532871489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	sram_ctrl_tl_intg_err	59825787945112246765362874743601120565202915992290209865300662089215112106024	308	UVM_ERROR @ 362230208 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between UVM_INFO @ 362230208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---