sysrst_ctrl Simulation Results

Simulation Results: sysrst_ctrl

11/01/2026 00:07:26 sha: 8eebaba json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
94.07 %

code
97.61 %

assert
98.08 %

func
86.52 %

line
98.85 %

branch
98.92 %

cond
97.98 %

toggle
100.00 %

FSM
92.31 %

Validation stages

V1		100.00%
V2		96.72%
V2S		95.56%
V3		92.00%

190/190 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	sysrst_ctrl_smoke	8.830s	2106.922us	50	50	100.00
input_output_inverted				50	50	100.00
	sysrst_ctrl_in_out_inverted	8.130s	2462.666us	50	50	100.00
combo_detect_ec_rst				5	5	100.00
	sysrst_ctrl_combo_detect_ec_rst	5.900s	2429.335us	5	5	100.00
combo_detect_ec_rst_with_pre_cond				5	5	100.00
	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	5.640s	2539.182us	5	5	100.00
csr_hw_reset				5	5	100.00
	sysrst_ctrl_csr_hw_reset	17.050s	6024.447us	5	5	100.00
csr_rw				20	20	100.00
	sysrst_ctrl_csr_rw	7.930s	2051.301us	20	20	100.00
csr_bit_bash				5	5	100.00
	sysrst_ctrl_csr_bit_bash	160.250s	41567.962us	5	5	100.00
csr_aliasing				5	5	100.00
	sysrst_ctrl_csr_aliasing	11.320s	3162.750us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	sysrst_ctrl_csr_mem_rw_with_rand_reset	9.040s	2071.379us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	sysrst_ctrl_csr_rw	7.930s	2051.301us	20	20	100.00
	sysrst_ctrl_csr_aliasing	11.320s	3162.750us	5	5	100.00

766/792 passed

96.72 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
combo_detect				50	50	100.00
	sysrst_ctrl_combo_detect	416.030s	151632.130us	50	50	100.00
combo_detect_with_pre_cond				92	100	92.00
	sysrst_ctrl_combo_detect_with_pre_cond	406.790s	193459.025us	92	100	92.00
auto_block_key_outputs				49	50	98.00
	sysrst_ctrl_auto_blk_key_output	1324.160s	549703.886us	49	50	98.00
keyboard_input_triggered_interrupt				45	50	90.00
	sysrst_ctrl_edge_detect	615.190s	391432.792us	45	50	90.00
pin_output_keyboard_inversion_control				50	50	100.00
	sysrst_ctrl_pin_override_test	10.370s	2511.469us	50	50	100.00
pin_input_value_accessibility				50	50	100.00
	sysrst_ctrl_pin_access_test	8.810s	2214.609us	50	50	100.00
ec_power_on_reset				50	50	100.00
	sysrst_ctrl_ec_pwr_on_rst	462.370s	214172.284us	50	50	100.00
flash_write_protect_output				50	50	100.00
	sysrst_ctrl_flash_wr_prot_out	10.260s	2612.446us	50	50	100.00
ultra_low_power_test				42	50	84.00
	sysrst_ctrl_ultra_low_pwr	535.410s	1512001.344us	42	50	84.00
sysrst_ctrl_feature_disable				2	2	100.00
	sysrst_ctrl_feature_disable	102.110s	41277.442us	2	2	100.00
stress_all				46	50	92.00
	sysrst_ctrl_stress_all	686.720s	320808.882us	46	50	92.00
alert_test				50	50	100.00
	sysrst_ctrl_alert_test	8.180s	2012.204us	50	50	100.00
intr_test				50	50	100.00
	sysrst_ctrl_intr_test	8.340s	2010.520us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	sysrst_ctrl_tl_errors	9.930s	2101.976us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	sysrst_ctrl_tl_errors	9.930s	2101.976us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	sysrst_ctrl_csr_hw_reset	17.050s	6024.447us	5	5	100.00
	sysrst_ctrl_csr_rw	7.930s	2051.301us	20	20	100.00
	sysrst_ctrl_csr_aliasing	11.320s	3162.750us	5	5	100.00
	sysrst_ctrl_same_csr_outstanding	35.140s	10157.190us	20	20	100.00
tl_d_partial_access				50	50	100.00
	sysrst_ctrl_csr_hw_reset	17.050s	6024.447us	5	5	100.00
	sysrst_ctrl_csr_rw	7.930s	2051.301us	20	20	100.00
	sysrst_ctrl_csr_aliasing	11.320s	3162.750us	5	5	100.00
	sysrst_ctrl_same_csr_outstanding	35.140s	10157.190us	20	20	100.00

V2S

43/45 passed

95.56 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				24	25	96.00
	sysrst_ctrl_tl_intg_err	130.480s	42413.128us	19	20	95.00
	sysrst_ctrl_sec_cm	111.590s	42013.890us	5	5	100.00
sec_cm_bus_integrity				19	20	95.00
	sysrst_ctrl_tl_intg_err	130.480s	42413.128us	19	20	95.00

46/50 passed

92.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				46	50	92.00
	sysrst_ctrl_stress_all_with_rand_reset	19.710s	5678.711us	46	50	92.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [sysrst_ctrl_common_vseq] expect alert:fatal_fault to fire
	sysrst_ctrl_tl_intg_err	19002409525099298522844349545708922684689151224021587256970545096403002616581	724	UVM_ERROR @ 22859312646 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 24914971090 ps: (cip_base_vseq__tl_errors.svh:388) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_intg_err_vseq 12/20 UVM_INFO @ 24938804328 ps: (cip_tl_seq_item.sv:117) uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq.tl_seq.req] TL data or integrity bits have been flipped, see the changes as below: a_addr: 0xce014b74 -> 0xce016b75 a_opcode: 0x1
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
	sysrst_ctrl_edge_detect	62722406701755242857527782540081750626507006724874200433160027523696887004387	648	UVM_ERROR @ 2625647111 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 2625730445 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 2625730445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	44004565230844221307123147303153667761923328606752826617928730135490945759468	647	UVM_ERROR @ 4914835013 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 4914855631 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 4914855631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	22105340628379519083153035206628378728463796369325730891113691880358857920617	647	UVM_ERROR @ 3189046902 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 3189067520 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 3189067520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	82417710414820959005584742957933609714387203876842802548893938378531739107289	663	UVM_ERROR @ 4311141151 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 4311161769 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 4311161769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	68056462443204536885073469745907196206910952681102060684009086169892166072793	651	UVM_ERROR @ 2569204084 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 2569284084 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 2569284084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	45159300540695058172128102806306716320504803832429050079076968381938513705981	656	UVM_ERROR @ 3021807334 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 3021827952 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 3021827952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_stress_all	94769878944437949379619168006247733106499219233822885342063964094674045739388	662	UVM_ERROR @ 213778436587 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 213778519921 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 213778519921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_stress_all	12579035166597117041621262055299168853879291359916772436338374092441634495602	649	UVM_ERROR @ 8859312374 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 8859354928 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 8859354928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	20301949496662862129524337764267648014863350664339971720949405132162357825315	648	UVM_ERROR @ 9852596129 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 9852676129 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 9852676129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_edge_detect	107351352756807144790167416674781813034827220536292319823239744715775304509954	652	UVM_ERROR @ 2583953562 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 2583994378 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 2583994378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_stress_all	96967692977413464597126774703898071994262393486513054527019912426201245570868	657	UVM_ERROR @ 5170755953 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 5170777005 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 5170777005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	43757218360687670564395629346876418380509376319926756354993817990057164020696	647	UVM_ERROR @ 8186963128 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 8187046462 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 8187046462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	77811958439493479170338759794193715893894623538315779797846364379386308246197	647	UVM_ERROR @ 3617758451 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 3617800117 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 3617800117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_stress_all_with_rand_reset	48743345876515850717223757895701646167580132620291673037402104053520351628007	664	UVM_ERROR @ 5929874924 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_ERROR @ 5929916590 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly UVM_INFO @ 5929916590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
	sysrst_ctrl_ultra_low_pwr	39147361927690846212198057279745366131103287550503254489954339974391428750580	647	UVM_ERROR @ 2176687525 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) UVM_INFO @ 2279187525 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i UVM_INFO @ 5994187525 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i UVM_INFO @ 8159187525 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check UVM_INFO @ 8180606159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
	sysrst_ctrl_ultra_low_pwr	65121436121306641003811675582807085765250382102449442902227166619492366357210	647	UVM_ERROR @ 4313152796 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) UVM_ERROR @ 5700652796 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0]) UVM_INFO @ 5700652796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_stress_all	49404181806328828061013434665044485076970265022649176435040516214546168317187	660	UVM_ERROR @ 9381931594 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) UVM_ERROR @ 632014431594 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0]) UVM_INFO @ 632014431594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_ultra_low_pwr	73091580508622405740828359635485876931067707260980403297188133784724082303549	647	UVM_ERROR @ 2596011120 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) UVM_ERROR @ 2703511120 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0]) UVM_INFO @ 2703511120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [] vs [*])
	sysrst_ctrl_combo_detect_with_pre_cond	4582197751869119967932722792626273292099858138022115604970350193110238412951	680	UVM_ERROR @ 38927665933 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 39047665933 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1 UVM_INFO @ 39067665933 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0 UVM_INFO @ 49174444176 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x24 UVM_INFO @ 49174527510 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x1a
	sysrst_ctrl_combo_detect_with_pre_cond	90896756950269969427982965468325897161478204546015435814556988244877641837522	659	UVM_ERROR @ 16981497470 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 28209848075 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0xe8 UVM_INFO @ 28209950115 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x2b UVM_INFO @ 29866855227 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1 UVM_INFO @ 29867100123 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(4) +/-*
	sysrst_ctrl_combo_detect_with_pre_cond	39783046346528968457097304741008439708077574000837300962268525171973439782341	672	UVM_ERROR @ 26392392954 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(4) +/-4 UVM_INFO @ 26482392954 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1 UVM_INFO @ 26502392954 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0 UVM_INFO @ 36568265395 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x14 UVM_INFO @ 36568306211 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x26
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-*
	sysrst_ctrl_combo_detect_with_pre_cond	33987171647596217367814942429742376406995564059165589020999453695994519715560	655	UVM_ERROR @ 13995768523 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-4 UVM_ERROR @ 13995768523 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(2) +/-4 UVM_INFO @ 13995768523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_combo_detect_with_pre_cond	71340379036877670898529580160120282419097421361052020215044376350768934687014	684	UVM_ERROR @ 40858492270 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-4 UVM_ERROR @ 40858492270 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(2) +/-4 UVM_INFO @ 40858492270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_pin_access_vseq.sv:35) [sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.pwrb_in == rdata_pwrb_in (* [] vs [*])
	sysrst_ctrl_stress_all_with_rand_reset	91619773575879802691197608090649951806536408050509272559472547799575990856005	673	UVM_ERROR @ 6775213299 ps: (sysrst_ctrl_pin_access_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.pwrb_in == rdata_pwrb_in (1 [0x1] vs 0 [0x0]) UVM_ERROR @ 6775213299 ps: (sysrst_ctrl_pin_access_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key0_in == rdata_key0_in (1 [0x1] vs 0 [0x0]) UVM_INFO @ 6775213299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_auto_blk_key_output_vseq.sv:119) [sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key1_out_value == cfg.vif.key1_out (* [] vs [*])
	sysrst_ctrl_auto_blk_key_output	6525904195846698367741735249221867865835201229828691094425670145884285161302	649	UVM_ERROR @ 2519003338 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key1_out_value == cfg.vif.key1_out (1 [0x1] vs 0 [0x0]) UVM_ERROR @ 2519003338 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key2_out_value == cfg.vif.key2_out (1 [0x1] vs 0 [0x0]) UVM_INFO @ 2519003338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [] vs [*])
	sysrst_ctrl_stress_all_with_rand_reset	101006512405093127511840161641528428074040929250897688041864105737763245925179	652	UVM_ERROR @ 4396570853 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:103) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (0 [0x0] vs 1 [0x1]) UVM_INFO @ 4400209901 ps: (cip_base_vseq.sv:1166) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Stress w/ reset is done for run 1/10 UVM_INFO @ 4412627580 ps: (cip_base_vseq.sv:1097) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 2/10 UVM_INFO @ 4412627580 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_errors_vseq 1/418
UVM_ERROR (sysrst_ctrl_pin_override_vseq.sv:27) [sysrst_ctrl_pin_override_vseq] Check failed out_val == * (* [] vs [*])
	sysrst_ctrl_stress_all_with_rand_reset	93853594873507934330170518878059913520110701934268689273875394852275760481795	659	UVM_ERROR @ 4075439146 ps: (sysrst_ctrl_pin_override_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_override_vseq] Check failed out_val == 0 (1 [0x1] vs 0 [0x0]) UVM_INFO @ 4077495950 ps: (cip_base_vseq.sv:1166) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Stress w/ reset is done for run 2/10 UVM_INFO @ 4082697353 ps: (cip_base_vseq.sv:1097) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 3/10 UVM_INFO @ 4082697353 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_tl_errors_vseq 1/330
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [] vs [*])
	sysrst_ctrl_combo_detect_with_pre_cond	60270203014826541040890360786889130940689093191936800273029501129210295630129	664	UVM_ERROR @ 25787728973 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1]) UVM_ERROR @ 25787728973 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 25787728973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_combo_detect_with_pre_cond	103537354630845862950606832242945863691813066797733396399137577458324409782827	681	UVM_ERROR @ 37779100433 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1]) UVM_ERROR @ 37779100433 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 37779100433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sysrst_ctrl_combo_detect_with_pre_cond	27640488862983955299855273123906335800497949043762876753026101865995358907361	699	UVM_ERROR @ 64866974382 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1]) UVM_ERROR @ 64866974382 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1]) UVM_INFO @ 64866974382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---