adc_ctrl Simulation Results

Simulation Results: adc_ctrl

18/01/2026 00:06:04 sha: 8ead910 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
95.13 %

code
98.74 %

assert
95.95 %

func
90.71 %

line
99.05 %

branch
98.64 %

cond
96.03 %

toggle
100.00 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		97.74%
V2S		100.00%
V3		94.00%

130/130 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	adc_ctrl_smoke	23.820s	6185.201us	50	50	100.00
csr_hw_reset				5	5	100.00
	adc_ctrl_csr_hw_reset	2.640s	1305.044us	5	5	100.00
csr_rw				20	20	100.00
	adc_ctrl_csr_rw	1.650s	522.872us	20	20	100.00
csr_bit_bash				5	5	100.00
	adc_ctrl_csr_bit_bash	129.630s	51748.652us	5	5	100.00
csr_aliasing				5	5	100.00
	adc_ctrl_csr_aliasing	2.900s	941.211us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	1.870s	485.211us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	adc_ctrl_csr_rw	1.650s	522.872us	20	20	100.00
	adc_ctrl_csr_aliasing	2.900s	941.211us	5	5	100.00

821/840 passed

97.74 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				50	50	100.00
	adc_ctrl_filters_polled	1056.620s	492276.422us	50	50	100.00
filters_polled_fixed				50	50	100.00
	adc_ctrl_filters_polled_fixed	1212.460s	493148.135us	50	50	100.00
filters_interrupt				49	50	98.00
	adc_ctrl_filters_interrupt	1207.140s	494670.638us	49	50	98.00
filters_interrupt_fixed				50	50	100.00
	adc_ctrl_filters_interrupt_fixed	1116.480s	492655.906us	50	50	100.00
filters_wakeup				50	50	100.00
	adc_ctrl_filters_wakeup	1377.570s	596369.179us	50	50	100.00
filters_wakeup_fixed				50	50	100.00
	adc_ctrl_filters_wakeup_fixed	1597.780s	604996.187us	50	50	100.00
filters_both				48	50	96.00
	adc_ctrl_filters_both	1163.370s	537049.561us	48	50	96.00
clock_gating				36	50	72.00
	adc_ctrl_clock_gating	1155.140s	561476.029us	36	50	72.00
poweron_counter				50	50	100.00
	adc_ctrl_poweron_counter	18.700s	5367.459us	50	50	100.00
lowpower_counter				50	50	100.00
	adc_ctrl_lowpower_counter	118.450s	39624.035us	50	50	100.00
fsm_reset				50	50	100.00
	adc_ctrl_fsm_reset	388.420s	126304.559us	50	50	100.00
stress_all				48	50	96.00
	adc_ctrl_stress_all	4363.660s	4138526.224us	48	50	96.00
alert_test				50	50	100.00
	adc_ctrl_alert_test	2.480s	516.268us	50	50	100.00
intr_test				50	50	100.00
	adc_ctrl_intr_test	1.490s	432.261us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	adc_ctrl_tl_errors	2.570s	783.381us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	adc_ctrl_tl_errors	2.570s	783.381us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	adc_ctrl_csr_hw_reset	2.640s	1305.044us	5	5	100.00
	adc_ctrl_csr_rw	1.650s	522.872us	20	20	100.00
	adc_ctrl_csr_aliasing	2.900s	941.211us	5	5	100.00
	adc_ctrl_same_csr_outstanding	8.610s	2579.158us	20	20	100.00
tl_d_partial_access				50	50	100.00
	adc_ctrl_csr_hw_reset	2.640s	1305.044us	5	5	100.00
	adc_ctrl_csr_rw	1.650s	522.872us	20	20	100.00
	adc_ctrl_csr_aliasing	2.900s	941.211us	5	5	100.00
	adc_ctrl_same_csr_outstanding	8.610s	2579.158us	20	20	100.00

V2S

45/45 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	adc_ctrl_tl_intg_err	18.580s	8926.398us	20	20	100.00
	adc_ctrl_sec_cm	28.240s	7939.756us	5	5	100.00
sec_cm_bus_integrity				20	20	100.00
	adc_ctrl_tl_intg_err	18.580s	8926.398us	20	20	100.00

47/50 passed

94.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				47	50	94.00
	adc_ctrl_stress_all_with_rand_reset	1481.430s	10000000.000us	47	50	94.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	adc_ctrl_clock_gating	37660952553411293781061841124760277875797627777849158144001356601942628662425	335	UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	115218849193775127015309403122053594551752349674071150837247161721340053834730	335	UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	80260775158293014842005735409527813976400863878646124408306534500122841471622	335	UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	57883280348455013677003113367315334877754297941811067913278589852593204680500	324	UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	80847491199111075914583959388896067289343934313443788067099372962122074289012	318	UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	58767607725811947458586036424329602894307560681762588263046660345845424793268	335	UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	62763328224511828567055637985592060951943258726440893704918276915880588946757	335	UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	5420099808794593165199998506773831917369771711752983860797995400347142864501	335	UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	16827701991582555914804300478362154900735182779375476178879643578786601591101	352	UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	99865635536104532967748580459878691656203848890020321835016221611847505847463	335	UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	22679138267520814959150649886177449993668997036226580134278597399755577299509	324	UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: adc_ctrl_reg_block.intr_state
	adc_ctrl_filters_interrupt	78777785977295526392656351083692835036871478179940070866361597744333858486192	334	UVM_ERROR @ 248805337178 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state UVM_INFO @ 248805337178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	93289154240641746148291027249553176842355228646813548229784214274492316599640	350	UVM_ERROR @ 435590298845 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state UVM_INFO @ 435590298845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	71944134437620323684158574254471136504536698517756110664394863621294814440611	334	UVM_ERROR @ 256507486420 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state UVM_INFO @ 256507486420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	43141786443188247921247109643908604833550550766357176700829287300739948187755	337	UVM_ERROR @ 247411657550 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state UVM_INFO @ 247411657550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
	adc_ctrl_clock_gating	105331717676315159091200113282686991886915107166837414474045307482535229539047	335	UVM_ERROR @ 167596710624 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_INFO @ 167596710624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	12817378801023730738381445073822228857903980941039038432000343275077576204678	337	UVM_ERROR @ 186597292119 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_INFO @ 186597292119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	83608833584292303013016121785321909480465963433015669204151943386831369512623	318	UVM_ERROR @ 5557100126 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_INFO @ 5557100126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	76840851789456820290892305383118169903789199355433419931467492306187216675263	405	UVM_ERROR @ 19787195793 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_INFO @ 19787195793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	96094417067993727286515195081953541164362067159655266346400239883250529626991	335	UVM_ERROR @ 162890745042 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_INFO @ 162890745042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	84954613295649701173876007982989132028357116271555013418743909572859966203855	335	UVM_ERROR @ 215801522485 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_INFO @ 215801522485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	18202316687382229485710006059711029545135178843419296503760410697473852847633	335	UVM_ERROR @ 171110678279 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error UVM_INFO @ 171110678279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---