| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 5 | 5 | 100.00 | |||
| aon_timer_smoke | 2.010s | 624.249us | 5 | 5 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| aon_timer_csr_hw_reset | 2.850s | 1279.793us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| aon_timer_csr_rw | 2.090s | 558.707us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| aon_timer_csr_bit_bash | 18.690s | 12070.866us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| aon_timer_csr_aliasing | 2.020s | 694.850us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| aon_timer_csr_mem_rw_with_rand_reset | 1.500s | 495.714us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| aon_timer_csr_rw | 2.090s | 558.707us | 20 | 20 | 100.00 | |
| aon_timer_csr_aliasing | 2.020s | 694.850us | 5 | 5 | 100.00 | |
| mem_walk | 5 | 5 | 100.00 | |||
| aon_timer_mem_walk | 1.890s | 438.570us | 5 | 5 | 100.00 | |
| mem_partial_access | 5 | 5 | 100.00 | |||
| aon_timer_mem_partial_access | 1.780s | 433.357us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prescaler | 15 | 15 | 100.00 | |||
| aon_timer_prescaler | 66.090s | 40564.363us | 15 | 15 | 100.00 | |
| jump | 5 | 5 | 100.00 | |||
| aon_timer_jump | 2.310s | 727.644us | 5 | 5 | 100.00 | |
| stress_all | 15 | 15 | 100.00 | |||
| aon_timer_stress_all | 149.460s | 107082.756us | 15 | 15 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| aon_timer_alert_test | 1.990s | 504.005us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| aon_timer_intr_test | 1.600s | 337.734us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| aon_timer_tl_errors | 3.050s | 516.493us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| aon_timer_tl_errors | 3.050s | 516.493us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| aon_timer_csr_hw_reset | 2.850s | 1279.793us | 5 | 5 | 100.00 | |
| aon_timer_csr_rw | 2.090s | 558.707us | 20 | 20 | 100.00 | |
| aon_timer_csr_aliasing | 2.020s | 694.850us | 5 | 5 | 100.00 | |
| aon_timer_same_csr_outstanding | 6.740s | 1767.432us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| aon_timer_csr_hw_reset | 2.850s | 1279.793us | 5 | 5 | 100.00 | |
| aon_timer_csr_rw | 2.090s | 558.707us | 20 | 20 | 100.00 | |
| aon_timer_csr_aliasing | 2.020s | 694.850us | 5 | 5 | 100.00 | |
| aon_timer_same_csr_outstanding | 6.740s | 1767.432us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| aon_timer_tl_intg_err | 16.480s | 8189.421us | 20 | 20 | 100.00 | |
| aon_timer_sec_cm | 5.760s | 4315.035us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| aon_timer_tl_intg_err | 16.480s | 8189.421us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_threshold | 5 | 5 | 100.00 | |||
| aon_timer_smoke_max_thold | 1.720s | 737.627us | 5 | 5 | 100.00 | |
| min_threshold | 5 | 5 | 100.00 | |||
| aon_timer_smoke_min_thold | 1.720s | 705.759us | 5 | 5 | 100.00 | |
| wkup_count_hi_cdc | 5 | 5 | 100.00 | |||
| aon_timer_wkup_count_cdc_hi | 7.320s | 3352.714us | 5 | 5 | 100.00 | |
| custom_intr | 10 | 10 | 100.00 | |||
| aon_timer_custom_intr | 2.810s | 720.149us | 10 | 10 | 100.00 | |
| alternating_on_off | 5 | 5 | 100.00 | |||
| aon_timer_alternating_enable_on_off | 19.270s | 4245.234us | 5 | 5 | 100.00 | |
| stress_all_with_rand_reset | 15 | 15 | 100.00 | |||
| aon_timer_stress_all_with_rand_reset | 38.340s | 16920.129us | 15 | 15 | 100.00 | |
| Test | seed | line | log context |
|---|