Simulation Results: chip

 
18/01/2026 00:06:04 sha: 8ead910 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.30 %
  • code
  • 86.34 %
  • assert
  • 97.25 %
  • func
  • 99.30 %
  • line
  • 94.74 %
  • branch
  • 94.69 %
  • cond
  • 93.46 %
  • toggle
  • 91.69 %
  • FSM
  • 57.14 %
Validation stages
V1
94.92%
V2
92.28%
V2S
66.67%
V3
84.85%
unmapped
77.27%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 12 12 100.00
chip_sw_example_flash 215.510s 3475.382us 3 3 100.00
chip_sw_example_rom 109.090s 2541.687us 3 3 100.00
chip_sw_example_manufacturer 159.190s 2305.977us 3 3 100.00
chip_sw_example_concurrency 189.040s 2886.671us 3 3 100.00
csr_hw_reset 5 5 100.00
chip_csr_hw_reset 344.330s 6872.625us 5 5 100.00
csr_rw 20 20 100.00
chip_csr_rw 534.610s 5773.618us 20 20 100.00
csr_bit_bash 5 5 100.00
chip_csr_bit_bash 3255.730s 59305.837us 5 5 100.00
csr_aliasing 5 5 100.00
chip_csr_aliasing 3470.510s 41092.897us 5 5 100.00
csr_mem_rw_with_rand_reset 7 20 35.00
chip_csr_mem_rw_with_rand_reset 756.290s 10438.351us 7 20 35.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
chip_csr_aliasing 3470.510s 41092.897us 5 5 100.00
chip_csr_rw 534.610s 5773.618us 20 20 100.00
xbar_smoke 100 100 100.00
xbar_smoke 11.740s 271.931us 100 100 100.00
chip_sw_gpio_out 3 3 100.00
chip_sw_gpio 352.600s 3449.761us 3 3 100.00
chip_sw_gpio_in 3 3 100.00
chip_sw_gpio 352.600s 3449.761us 3 3 100.00
chip_sw_gpio_irq 3 3 100.00
chip_sw_gpio 352.600s 3449.761us 3 3 100.00
chip_sw_uart_tx_rx 5 5 100.00
chip_sw_uart_tx_rx 483.760s 4344.000us 5 5 100.00
chip_sw_uart_rx_overflow 20 20 100.00
chip_sw_uart_tx_rx 483.760s 4344.000us 5 5 100.00
chip_sw_uart_tx_rx_idx1 495.790s 3972.953us 5 5 100.00
chip_sw_uart_tx_rx_idx2 485.350s 4427.139us 5 5 100.00
chip_sw_uart_tx_rx_idx3 492.560s 4170.296us 5 5 100.00
chip_sw_uart_baud_rate 20 20 100.00
chip_sw_uart_rand_baudrate 2250.250s 13523.085us 20 20 100.00
chip_sw_uart_tx_rx_alt_clk_freq 10 10 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2085.950s 13296.745us 5 5 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 1478.670s 13727.189us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 10 10 100.00
chip_padctrl_attributes 266.880s 5355.125us 10 10 100.00
chip_padctrl_attributes 10 10 100.00
chip_padctrl_attributes 266.880s 5355.125us 10 10 100.00
chip_sw_sleep_pin_mio_dio_val 2 3 66.67
chip_sw_sleep_pin_mio_dio_val 228.400s 2898.295us 2 3 66.67
chip_sw_sleep_pin_wake 3 3 100.00
chip_sw_sleep_pin_wake 323.390s 5120.904us 3 3 100.00
chip_sw_sleep_pin_retention 3 3 100.00
chip_sw_sleep_pin_retention 254.120s 4666.132us 3 3 100.00
chip_sw_tap_strap_sampling 20 20 100.00
chip_tap_straps_dev 1108.020s 14488.905us 5 5 100.00
chip_tap_straps_testunlock0 373.050s 5563.890us 5 5 100.00
chip_tap_straps_rma 273.840s 4520.211us 5 5 100.00
chip_tap_straps_prod 1310.350s 18200.556us 5 5 100.00
chip_sw_pattgen_ios 3 3 100.00
chip_sw_pattgen_ios 201.120s 3407.811us 3 3 100.00
chip_sw_sleep_pwm_pulses 3 3 100.00
chip_sw_sleep_pwm_pulses 1067.780s 8650.114us 3 3 100.00
chip_sw_data_integrity 6 6 100.00
chip_sw_data_integrity_escalation 601.800s 5978.642us 6 6 100.00
chip_sw_instruction_integrity 6 6 100.00
chip_sw_data_integrity_escalation 601.800s 5978.642us 6 6 100.00
chip_sw_ast_clk_outputs 3 3 100.00
chip_sw_ast_clk_outputs 775.470s 8132.119us 3 3 100.00
chip_sw_ast_clk_rst_inputs 1 3 33.33
chip_sw_ast_clk_rst_inputs 4095.810s 27853.841us 1 3 33.33
chip_sw_ast_sys_clk_jitter 30 30 100.00
chip_sw_flash_ctrl_ops_jitter_en 505.400s 4415.633us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 754.780s 5695.372us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3975.820s 18570.308us 3 3 100.00
chip_sw_aes_enc_jitter_en 270.150s 3684.874us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 918.730s 6823.291us 3 3 100.00
chip_sw_hmac_enc_jitter_en 259.610s 3307.976us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 1478.030s 10357.308us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 253.160s 3717.047us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 518.510s 5774.451us 3 3 100.00
chip_sw_clkmgr_jitter 196.130s 2350.837us 3 3 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 178.550s 3223.697us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 7 8 87.50
chip_sw_sensor_ctrl_alert 845.670s 8692.510us 4 5 80.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 359.150s 5792.877us 3 3 100.00
chip_sw_sensor_ctrl_ast_status 3 3 100.00
chip_sw_sensor_ctrl_status 233.030s 3044.859us 3 3 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 3 3 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 359.150s 5792.877us 3 3 100.00
chip_sw_smoketest 51 51 100.00
chip_sw_flash_scrambling_smoketest 190.640s 2603.947us 3 3 100.00
chip_sw_aes_smoketest 236.210s 3563.326us 3 3 100.00
chip_sw_aon_timer_smoketest 272.700s 3417.438us 3 3 100.00
chip_sw_clkmgr_smoketest 191.200s 3082.517us 3 3 100.00
chip_sw_csrng_smoketest 196.660s 3230.144us 3 3 100.00
chip_sw_entropy_src_smoketest 1151.170s 7073.087us 3 3 100.00
chip_sw_gpio_smoketest 226.920s 3553.224us 3 3 100.00
chip_sw_hmac_smoketest 243.660s 3237.350us 3 3 100.00
chip_sw_kmac_smoketest 288.890s 2915.302us 3 3 100.00
chip_sw_otbn_smoketest 1448.360s 8477.038us 3 3 100.00
chip_sw_pwrmgr_smoketest 387.800s 6425.591us 3 3 100.00
chip_sw_pwrmgr_usbdev_smoketest 432.180s 6875.210us 3 3 100.00
chip_sw_rv_plic_smoketest 223.100s 2553.982us 3 3 100.00
chip_sw_rv_timer_smoketest 217.300s 3095.912us 3 3 100.00
chip_sw_rstmgr_smoketest 178.650s 2768.031us 3 3 100.00
chip_sw_sram_ctrl_smoketest 195.120s 2340.022us 3 3 100.00
chip_sw_uart_smoketest 251.490s 3497.956us 3 3 100.00
chip_sw_otp_smoketest 3 3 100.00
chip_sw_otp_ctrl_smoketest 191.540s 3114.143us 3 3 100.00
chip_sw_rom_functests 0 3 0.00
rom_keymgr_functest 529.680s 5190.755us 0 3 0.00
chip_sw_boot 3 3 100.00
chip_sw_uart_tx_rx_bootstrap 12144.200s 61688.288us 3 3 100.00
chip_sw_secure_boot 3 3 100.00
rom_e2e_smoke 3615.290s 15486.838us 3 3 100.00
chip_sw_rom_raw_unlock 1 3 33.33
rom_raw_unlock 1059.390s 15204.845us 1 3 33.33
chip_sw_power_idle_load 0 3 0.00
chip_sw_power_idle_load 223.390s 3412.363us 0 3 0.00
chip_sw_power_sleep_load 0 3 0.00
chip_sw_power_sleep_load 232.260s 3692.876us 0 3 0.00
chip_sw_exit_test_unlocked_bootstrap 3 3 100.00
chip_sw_exit_test_unlocked_bootstrap 10427.590s 54909.878us 3 3 100.00
chip_sw_inject_scramble_seed 3 3 100.00
chip_sw_inject_scramble_seed 11702.490s 57399.294us 3 3 100.00
tl_d_oob_addr_access 1 30 3.33
chip_tl_errors 206.230s 3875.259us 1 30 3.33
tl_d_illegal_access 1 30 3.33
chip_tl_errors 206.230s 3875.259us 1 30 3.33
tl_d_outstanding_access 50 50 100.00
chip_csr_aliasing 3470.510s 41092.897us 5 5 100.00
chip_same_csr_outstanding 2387.270s 30957.493us 20 20 100.00
chip_csr_hw_reset 344.330s 6872.625us 5 5 100.00
chip_csr_rw 534.610s 5773.618us 20 20 100.00
tl_d_partial_access 50 50 100.00
chip_csr_aliasing 3470.510s 41092.897us 5 5 100.00
chip_same_csr_outstanding 2387.270s 30957.493us 20 20 100.00
chip_csr_hw_reset 344.330s 6872.625us 5 5 100.00
chip_csr_rw 534.610s 5773.618us 20 20 100.00
xbar_base_random_sequence 100 100 100.00
xbar_random 78.530s 2449.158us 100 100 100.00
xbar_random_delay 600 600 100.00
xbar_smoke_zero_delays 7.900s 53.354us 100 100 100.00
xbar_smoke_large_delays 98.160s 10343.090us 100 100 100.00
xbar_smoke_slow_rsp 91.940s 5689.687us 100 100 100.00
xbar_random_zero_delays 51.420s 591.463us 100 100 100.00
xbar_random_large_delays 470.490s 51710.332us 100 100 100.00
xbar_random_slow_rsp 404.810s 35587.880us 100 100 100.00
xbar_unmapped_address 200 200 100.00
xbar_unmapped_addr 53.730s 1569.974us 100 100 100.00
xbar_error_and_unmapped_addr 56.160s 1388.651us 100 100 100.00
xbar_error_cases 200 200 100.00
xbar_error_random 75.980s 2504.929us 100 100 100.00
xbar_error_and_unmapped_addr 56.160s 1388.651us 100 100 100.00
xbar_all_access_same_device 200 200 100.00
xbar_access_same_device 135.830s 3650.080us 100 100 100.00
xbar_access_same_device_slow_rsp 886.180s 81657.277us 100 100 100.00
xbar_all_hosts_use_same_source_id 100 100 100.00
xbar_same_source 62.360s 2724.360us 100 100 100.00
xbar_stress_all 200 200 100.00
xbar_stress_all 484.780s 15536.942us 100 100 100.00
xbar_stress_all_with_error 440.900s 16423.816us 100 100 100.00
xbar_stress_with_reset 200 200 100.00
xbar_stress_all_with_rand_reset 714.950s 22085.267us 100 100 100.00
xbar_stress_all_with_reset_error 794.120s 28812.011us 100 100 100.00
rom_e2e_smoke 3 3 100.00
rom_e2e_smoke 3615.290s 15486.838us 3 3 100.00
rom_e2e_shutdown_output 3 3 100.00
rom_e2e_shutdown_output 3383.620s 29096.570us 3 3 100.00
rom_e2e_shutdown_exception_c 3 3 100.00
rom_e2e_shutdown_exception_c 3547.460s 15084.008us 3 3 100.00
rom_e2e_boot_policy_valid 4 15 26.67
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2695.100s 12336.087us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 3759.850s 20220.857us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 3648.400s 15261.454us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 3555.110s 15787.810us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 3407.670s 14709.454us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 19.120s 10.120us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 22.670s 10.320us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 22.360s 10.260us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 27.630s 10.260us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 24.810s 10.240us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 17.660s 10.260us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 22.210s 10.240us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 18.000s 10.220us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 17.390s 10.400us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 16.960s 10.240us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 24.740s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 20.900s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 17.030s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 17.650s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 20.190s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 18.610s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 18.140s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 19.850s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 24.560s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 16.290s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 27.750s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 18.350s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 30.410s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 17.550s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 18.710s 10.100us 0 1 0.00
rom_e2e_asm_init 15 15 100.00
rom_e2e_asm_init_test_unlocked0 2800.160s 11935.213us 3 3 100.00
rom_e2e_asm_init_dev 3800.820s 16534.821us 3 3 100.00
rom_e2e_asm_init_prod 3669.650s 15750.013us 3 3 100.00
rom_e2e_asm_init_prod_end 3622.520s 15149.437us 3 3 100.00
rom_e2e_asm_init_rma 3685.480s 17688.379us 3 3 100.00
rom_e2e_keymgr_init 6 9 66.67
rom_e2e_keymgr_init_rom_ext_meas 7191.630s 29462.992us 2 3 66.67
rom_e2e_keymgr_init_rom_ext_no_meas 7424.840s 31460.460us 2 3 66.67
rom_e2e_keymgr_init_rom_ext_invalid_meas 6923.080s 29770.359us 2 3 66.67
rom_e2e_static_critical 3 3 100.00
rom_e2e_static_critical 3899.000s 16832.128us 3 3 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0.000s 0.000us 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0.000s 0.000us 0 3 0.00
chip_sw_aes_enc 6 6 100.00
chip_sw_aes_enc 211.570s 2505.806us 3 3 100.00
chip_sw_aes_enc_jitter_en 270.150s 3684.874us 3 3 100.00
chip_sw_aes_entropy 3 3 100.00
chip_sw_aes_entropy 189.910s 2743.438us 3 3 100.00
chip_sw_aes_idle 3 3 100.00
chip_sw_aes_idle 210.210s 3173.356us 3 3 100.00
chip_sw_aes_sideload 3 3 100.00
chip_sw_keymgr_sideload_aes 1635.590s 9606.487us 3 3 100.00
chip_sw_alert_handler_alerts 0 3 0.00
chip_sw_alert_test 221.170s 2999.470us 0 3 0.00
chip_sw_alert_handler_escalations 3 3 100.00
chip_sw_alert_handler_escalation 481.110s 4820.663us 3 3 100.00
chip_sw_all_escalation_resets 94 100 94.00
chip_sw_all_escalation_resets 626.340s 5801.425us 94 100 94.00
chip_sw_alert_handler_irqs 9 9 100.00
chip_plic_all_irqs_0 706.370s 5958.537us 3 3 100.00
chip_plic_all_irqs_10 363.380s 3833.475us 3 3 100.00
chip_plic_all_irqs_20 390.220s 3714.893us 3 3 100.00
chip_sw_alert_handler_entropy 3 3 100.00
chip_sw_alert_handler_entropy 310.900s 3394.592us 3 3 100.00
chip_sw_alert_handler_crashdump 3 3 100.00
chip_sw_rstmgr_alert_info 1483.230s 13911.120us 3 3 100.00
chip_sw_alert_handler_ping_timeout 3 3 100.00
chip_sw_alert_handler_ping_timeout 411.090s 5073.361us 3 3 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 233.230s 2564.398us 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 3 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 3 0.00
chip_sw_alert_handler_lpg_clock_off 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 1191.290s 7462.915us 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 1364.390s 8015.324us 3 3 100.00
chip_sw_alert_handler_ping_ok 3 3 100.00
chip_sw_alert_handler_ping_ok 1083.710s 7825.547us 3 3 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 3 3 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 13218.510s 256231.370us 3 3 100.00
chip_sw_aon_timer_wakeup_irq 3 3 100.00
chip_sw_aon_timer_irq 285.400s 3762.469us 3 3 100.00
chip_sw_aon_timer_sleep_wakeup 3 3 100.00
chip_sw_pwrmgr_smoketest 387.800s 6425.591us 3 3 100.00
chip_sw_aon_timer_wdog_bark_irq 3 3 100.00
chip_sw_aon_timer_irq 285.400s 3762.469us 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 2 3 66.67
chip_sw_aon_timer_wdog_bite_reset 655.970s 7676.786us 2 3 66.67
chip_sw_aon_timer_sleep_wdog_bite_reset 2 3 66.67
chip_sw_aon_timer_wdog_bite_reset 655.970s 7676.786us 2 3 66.67
chip_sw_aon_timer_sleep_wdog_sleep_pause 5 5 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 366.100s 7457.857us 5 5 100.00
chip_sw_aon_timer_wdog_lc_escalate 3 3 100.00
chip_sw_aon_timer_wdog_lc_escalate 531.330s 5812.120us 3 3 100.00
chip_sw_clkmgr_idle_trans 12 12 100.00
chip_sw_otbn_randomness 738.660s 6646.862us 3 3 100.00
chip_sw_aes_idle 210.210s 3173.356us 3 3 100.00
chip_sw_hmac_enc_idle 247.950s 3300.237us 3 3 100.00
chip_sw_kmac_idle 180.530s 2479.264us 3 3 100.00
chip_sw_clkmgr_off_trans 12 12 100.00
chip_sw_clkmgr_off_aes_trans 413.310s 4770.716us 3 3 100.00
chip_sw_clkmgr_off_hmac_trans 389.390s 4188.012us 3 3 100.00
chip_sw_clkmgr_off_kmac_trans 283.270s 3728.468us 3 3 100.00
chip_sw_clkmgr_off_otbn_trans 372.490s 4791.522us 3 3 100.00
chip_sw_clkmgr_off_peri 3 3 100.00
chip_sw_clkmgr_off_peri 1128.630s 11553.513us 3 3 100.00
chip_sw_clkmgr_div 21 21 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 517.330s 4272.991us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 478.160s 4505.045us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 488.140s 4722.057us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 520.590s 4608.200us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 484.820s 3899.067us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 543.310s 5099.939us 3 3 100.00
chip_sw_ast_clk_outputs 775.470s 8132.119us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 512.370s 12151.765us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw 6 6 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 488.140s 4722.057us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 520.590s 4608.200us 3 3 100.00
chip_sw_clkmgr_jitter 30 30 100.00
chip_sw_flash_ctrl_ops_jitter_en 505.400s 4415.633us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 754.780s 5695.372us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3975.820s 18570.308us 3 3 100.00
chip_sw_aes_enc_jitter_en 270.150s 3684.874us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 918.730s 6823.291us 3 3 100.00
chip_sw_hmac_enc_jitter_en 259.610s 3307.976us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 1478.030s 10357.308us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 253.160s 3717.047us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 518.510s 5774.451us 3 3 100.00
chip_sw_clkmgr_jitter 196.130s 2350.837us 3 3 100.00
chip_sw_clkmgr_extended_range 33 33 100.00
chip_sw_clkmgr_jitter_reduced_freq 173.480s 3458.157us 3 3 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 499.190s 4599.252us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 827.560s 7621.975us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4557.000s 24766.825us 3 3 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 207.770s 3813.460us 3 3 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 200.840s 3280.480us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1179.330s 10827.002us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 272.530s 3365.579us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 409.090s 4614.479us 3 3 100.00
chip_sw_flash_init_reduced_freq 1631.270s 24272.196us 3 3 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 20432.790s 176334.279us 3 3 100.00
chip_sw_clkmgr_deep_sleep_frequency 3 3 100.00
chip_sw_ast_clk_outputs 775.470s 8132.119us 3 3 100.00
chip_sw_clkmgr_sleep_frequency 3 3 100.00
chip_sw_clkmgr_sleep_frequency 427.180s 4871.503us 3 3 100.00
chip_sw_clkmgr_reset_frequency 3 3 100.00
chip_sw_clkmgr_reset_frequency 288.690s 3488.208us 3 3 100.00
chip_sw_clkmgr_escalation_reset 94 100 94.00
chip_sw_all_escalation_resets 626.340s 5801.425us 94 100 94.00
chip_sw_clkmgr_alert_handler_clock_enables 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 1191.290s 7462.915us 3 3 100.00
chip_sw_csrng_edn_cmd 3 3 100.00
chip_sw_entropy_src_csrng 1380.050s 8296.814us 3 3 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 3 33.33
chip_sw_csrng_fuse_en_sw_app_read_test 392.330s 4871.725us 1 3 33.33
chip_sw_csrng_lc_hw_debug_en 3 3 100.00
chip_sw_csrng_lc_hw_debug_en_test 536.310s 5941.129us 3 3 100.00
chip_sw_csrng_known_answer_tests 3 3 100.00
chip_sw_csrng_kat_test 270.910s 2885.241us 3 3 100.00
chip_sw_edn_entropy_reqs 16 16 100.00
chip_sw_csrng_edn_concurrency 6095.660s 27204.439us 10 10 100.00
chip_sw_entropy_src_ast_rng_req 188.250s 3469.226us 3 3 100.00
chip_sw_edn_entropy_reqs 1022.110s 7665.357us 3 3 100.00
chip_sw_entropy_src_ast_rng_req 3 3 100.00
chip_sw_entropy_src_ast_rng_req 188.250s 3469.226us 3 3 100.00
chip_sw_entropy_src_csrng 3 3 100.00
chip_sw_entropy_src_csrng 1380.050s 8296.814us 3 3 100.00
chip_sw_entropy_src_known_answer_tests 3 3 100.00
chip_sw_entropy_src_kat_test 209.020s 2962.579us 3 3 100.00
chip_sw_flash_init 3 3 100.00
chip_sw_flash_init 1769.180s 25082.678us 3 3 100.00
chip_sw_flash_host_access 6 6 100.00
chip_sw_flash_ctrl_access 710.900s 5032.935us 3 3 100.00
chip_sw_flash_ctrl_access_jitter_en 754.780s 5695.372us 3 3 100.00
chip_sw_flash_ctrl_ops 6 6 100.00
chip_sw_flash_ctrl_ops 389.470s 4059.778us 3 3 100.00
chip_sw_flash_ctrl_ops_jitter_en 505.400s 4415.633us 3 3 100.00
chip_sw_flash_rma_unlocked 3 3 100.00
chip_sw_flash_rma_unlocked 4781.000s 45007.745us 3 3 100.00
chip_sw_flash_scramble 3 3 100.00
chip_sw_flash_init 1769.180s 25082.678us 3 3 100.00
chip_sw_flash_idle_low_power 3 3 100.00
chip_sw_flash_ctrl_idle_low_power 242.950s 3503.350us 3 3 100.00
chip_sw_flash_keymgr_seeds 3 3 100.00
chip_sw_keymgr_key_derivation 1926.990s 11987.314us 3 3 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 3 3 100.00
chip_sw_flash_ctrl_lc_rw_en 390.840s 4148.024us 3 3 100.00
chip_sw_flash_creator_seed_wipe_on_rma 3 3 100.00
chip_sw_flash_rma_unlocked 4781.000s 45007.745us 3 3 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 3 3 100.00
chip_sw_flash_ctrl_lc_rw_en 390.840s 4148.024us 3 3 100.00
chip_sw_flash_lc_iso_part_sw_rd_en 3 3 100.00
chip_sw_flash_ctrl_lc_rw_en 390.840s 4148.024us 3 3 100.00
chip_sw_flash_lc_iso_part_sw_wr_en 3 3 100.00
chip_sw_flash_ctrl_lc_rw_en 390.840s 4148.024us 3 3 100.00
chip_sw_flash_lc_seed_hw_rd_en 3 3 100.00
chip_sw_flash_ctrl_lc_rw_en 390.840s 4148.024us 3 3 100.00
chip_sw_flash_lc_escalate_en 94 100 94.00
chip_sw_all_escalation_resets 626.340s 5801.425us 94 100 94.00
chip_sw_flash_prim_tl_access 3 3 100.00
chip_prim_tl_access 487.350s 12178.521us 3 3 100.00
chip_sw_flash_ctrl_clock_freqs 3 3 100.00
chip_sw_flash_ctrl_clock_freqs 778.350s 5582.954us 3 3 100.00
chip_sw_flash_ctrl_escalation_reset 3 3 100.00
chip_sw_flash_crash_alert 518.380s 5543.185us 3 3 100.00
chip_sw_flash_ctrl_write_clear 3 3 100.00
chip_sw_flash_crash_alert 518.380s 5543.185us 3 3 100.00
chip_sw_hmac_enc 6 6 100.00
chip_sw_hmac_enc 229.490s 2764.927us 3 3 100.00
chip_sw_hmac_enc_jitter_en 259.610s 3307.976us 3 3 100.00
chip_sw_hmac_idle 3 3 100.00
chip_sw_hmac_enc_idle 247.950s 3300.237us 3 3 100.00
chip_sw_hmac_all_configurations 2 3 66.67
chip_sw_hmac_oneshot 1985.240s 11134.048us 2 3 66.67
chip_sw_hmac_multistream_mode 3 3 100.00
chip_sw_hmac_multistream 898.500s 5243.336us 3 3 100.00
chip_sw_i2c_host_tx_rx 9 9 100.00
chip_sw_i2c_host_tx_rx 571.570s 4627.611us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx1 578.720s 5679.626us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx2 541.170s 5365.128us 3 3 100.00
chip_sw_i2c_device_tx_rx 3 3 100.00
chip_sw_i2c_device_tx_rx 341.230s 3698.695us 3 3 100.00
chip_sw_keymgr_key_derivation 6 6 100.00
chip_sw_keymgr_key_derivation 1926.990s 11987.314us 3 3 100.00
chip_sw_keymgr_key_derivation_jitter_en 1478.030s 10357.308us 3 3 100.00
chip_sw_keymgr_sideload_kmac 3 3 100.00
chip_sw_keymgr_sideload_kmac 1583.610s 10663.321us 3 3 100.00
chip_sw_keymgr_sideload_aes 3 3 100.00
chip_sw_keymgr_sideload_aes 1635.590s 9606.487us 3 3 100.00
chip_sw_keymgr_sideload_otbn 3 3 100.00
chip_sw_keymgr_sideload_otbn 3511.450s 15842.271us 3 3 100.00
chip_sw_kmac_enc 9 9 100.00
chip_sw_kmac_mode_cshake 228.110s 3369.942us 3 3 100.00
chip_sw_kmac_mode_kmac 248.600s 3214.216us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 253.160s 3717.047us 3 3 100.00
chip_sw_kmac_app_keymgr 3 3 100.00
chip_sw_keymgr_key_derivation 1926.990s 11987.314us 3 3 100.00
chip_sw_kmac_app_lc 15 15 100.00
chip_sw_lc_ctrl_transition 969.880s 14061.950us 15 15 100.00
chip_sw_kmac_app_rom 3 3 100.00
chip_sw_kmac_app_rom 168.220s 2915.604us 3 3 100.00
chip_sw_kmac_entropy 3 3 100.00
chip_sw_kmac_entropy 1928.160s 10050.693us 3 3 100.00
chip_sw_kmac_idle 3 3 100.00
chip_sw_kmac_idle 180.530s 2479.264us 3 3 100.00
chip_sw_lc_ctrl_alert_handler_escalation 3 3 100.00
chip_sw_alert_handler_escalation 481.110s 4820.663us 3 3 100.00
chip_sw_lc_ctrl_jtag_access 15 15 100.00
chip_tap_straps_dev 1108.020s 14488.905us 5 5 100.00
chip_tap_straps_rma 273.840s 4520.211us 5 5 100.00
chip_tap_straps_prod 1310.350s 18200.556us 5 5 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 183.350s 3219.785us 3 3 100.00
chip_sw_lc_ctrl_init 15 15 100.00
chip_sw_lc_ctrl_transition 969.880s 14061.950us 15 15 100.00
chip_sw_lc_ctrl_transitions 15 15 100.00
chip_sw_lc_ctrl_transition 969.880s 14061.950us 15 15 100.00
chip_sw_lc_ctrl_kmac_req 15 15 100.00
chip_sw_lc_ctrl_transition 969.880s 14061.950us 15 15 100.00
chip_sw_lc_ctrl_key_div 3 3 100.00
chip_sw_keymgr_key_derivation_prod 2118.540s 12309.090us 3 3 100.00
chip_sw_lc_ctrl_broadcast 78 84 92.86
chip_sw_flash_ctrl_lc_rw_en 390.840s 4148.024us 3 3 100.00
chip_sw_flash_rma_unlocked 4781.000s 45007.745us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 242.920s 3172.796us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 724.200s 7754.760us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 685.500s 6933.757us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 562.490s 6440.013us 0 3 0.00
chip_sw_lc_ctrl_transition 969.880s 14061.950us 15 15 100.00
chip_sw_keymgr_key_derivation 1926.990s 11987.314us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 390.560s 9535.392us 3 3 100.00
chip_sw_sram_ctrl_execution_main 551.610s 8311.839us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 512.370s 12151.765us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 517.330s 4272.991us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 478.160s 4505.045us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 488.140s 4722.057us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 520.590s 4608.200us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 484.820s 3899.067us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 543.310s 5099.939us 3 3 100.00
chip_tap_straps_dev 1108.020s 14488.905us 5 5 100.00
chip_tap_straps_rma 273.840s 4520.211us 5 5 100.00
chip_tap_straps_prod 1310.350s 18200.556us 5 5 100.00
chip_prim_tl_access 487.350s 12178.521us 3 3 100.00
chip_rv_dm_lc_disabled 194.800s 6008.722us 0 3 0.00
chip_lc_scrap 6 6 100.00
chip_sw_lc_ctrl_rma_to_scrap 125.980s 2810.779us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 111.670s 2720.441us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 133.050s 3578.681us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 231.790s 3433.748us 3 3 100.00
chip_lc_test_locked 3 6 50.00
chip_sw_lc_walkthrough_testunlocks 1804.500s 27623.689us 3 3 100.00
chip_rv_dm_lc_disabled 194.800s 6008.722us 0 3 0.00
chip_sw_lc_walkthrough 15 15 100.00
chip_sw_lc_walkthrough_dev 5294.360s 50807.978us 3 3 100.00
chip_sw_lc_walkthrough_prod 5572.630s 50195.732us 3 3 100.00
chip_sw_lc_walkthrough_prodend 757.940s 9243.394us 3 3 100.00
chip_sw_lc_walkthrough_rma 5055.170s 45766.554us 3 3 100.00
chip_sw_lc_walkthrough_testunlocks 1804.500s 27623.689us 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 9 9 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 88.440s 2108.817us 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 107.410s 2988.374us 3 3 100.00
rom_volatile_raw_unlock 101.180s 2560.546us 3 3 100.00
chip_sw_otbn_op 6 6 100.00
chip_sw_otbn_ecdsa_op_irq 4015.180s 16656.383us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3975.820s 18570.308us 3 3 100.00
chip_sw_otbn_rnd_entropy 3 3 100.00
chip_sw_otbn_randomness 738.660s 6646.862us 3 3 100.00
chip_sw_otbn_urnd_entropy 3 3 100.00
chip_sw_otbn_randomness 738.660s 6646.862us 3 3 100.00
chip_sw_otbn_idle 3 3 100.00
chip_sw_otbn_randomness 738.660s 6646.862us 3 3 100.00
chip_sw_otbn_mem_scramble 3 3 100.00
chip_sw_otbn_mem_scramble 399.660s 3464.168us 3 3 100.00
chip_otp_ctrl_init 15 15 100.00
chip_sw_lc_ctrl_transition 969.880s 14061.950us 15 15 100.00
chip_sw_otp_ctrl_keys 15 15 100.00
chip_sw_flash_init 1769.180s 25082.678us 3 3 100.00
chip_sw_otbn_mem_scramble 399.660s 3464.168us 3 3 100.00
chip_sw_keymgr_key_derivation 1926.990s 11987.314us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 502.090s 5491.270us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 175.230s 2492.032us 3 3 100.00
chip_sw_otp_ctrl_entropy 15 15 100.00
chip_sw_flash_init 1769.180s 25082.678us 3 3 100.00
chip_sw_otbn_mem_scramble 399.660s 3464.168us 3 3 100.00
chip_sw_keymgr_key_derivation 1926.990s 11987.314us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 502.090s 5491.270us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 175.230s 2492.032us 3 3 100.00
chip_sw_otp_ctrl_program 15 15 100.00
chip_sw_lc_ctrl_transition 969.880s 14061.950us 15 15 100.00
chip_sw_otp_ctrl_program_error 3 3 100.00
chip_sw_lc_ctrl_program_error 482.930s 5311.251us 3 3 100.00
chip_sw_otp_ctrl_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 183.350s 3219.785us 3 3 100.00
chip_sw_otp_ctrl_lc_signals 27 30 90.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 242.920s 3172.796us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 724.200s 7754.760us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 685.500s 6933.757us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 562.490s 6440.013us 0 3 0.00
chip_sw_lc_ctrl_transition 969.880s 14061.950us 15 15 100.00
chip_prim_tl_access 487.350s 12178.521us 3 3 100.00
chip_sw_otp_prim_tl_access 3 3 100.00
chip_prim_tl_access 487.350s 12178.521us 3 3 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 898.460s 6166.382us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 3 3 100.00
chip_sw_pwrmgr_full_aon_reset 414.470s 6638.249us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1811.250s 27997.757us 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 381.600s 7461.820us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 1 3 33.33
chip_sw_pwrmgr_deep_sleep_por_reset 470.420s 8101.940us 1 3 33.33
chip_sw_pwrmgr_normal_sleep_por_reset 3 3 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 599.820s 7248.018us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1230.720s 26334.593us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 4 6 66.67
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1108.450s 13938.259us 2 3 66.67
chip_sw_aon_timer_wdog_bite_reset 655.970s 7676.786us 2 3 66.67
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1128.530s 13416.693us 3 3 100.00
chip_sw_pwrmgr_wdog_reset 3 3 100.00
chip_sw_pwrmgr_wdog_reset 386.370s 4087.956us 3 3 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_full_aon_reset 414.470s 6638.249us 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 410.840s 4839.549us 3 3 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 3 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1309.600s 23451.632us 0 3 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 424.160s 6961.444us 3 3 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 377.030s 5920.478us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 523.210s 10978.867us 0 3 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 6 6 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 978.890s 8235.642us 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 1075.680s 11199.907us 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2259.270s 29105.630us 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 235.750s 2845.389us 3 3 100.00
chip_sw_pwrmgr_escalation_reset 94 100 94.00
chip_sw_all_escalation_resets 626.340s 5801.425us 94 100 94.00
chip_sw_rom_access 3 3 100.00
chip_sw_rom_ctrl_integrity_check 390.560s 9535.392us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 3 3 100.00
chip_sw_rom_ctrl_integrity_check 390.560s 9535.392us 3 3 100.00
chip_sw_rstmgr_non_sys_reset_info 9 12 75.00
chip_sw_pwrmgr_all_reset_reqs 1075.680s 11199.907us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 523.210s 10978.867us 0 3 0.00
chip_sw_pwrmgr_wdog_reset 386.370s 4087.956us 3 3 100.00
chip_sw_pwrmgr_smoketest 387.800s 6425.591us 3 3 100.00
chip_sw_rstmgr_sys_reset_info 3 3 100.00
chip_rv_dm_ndm_reset_req 363.530s 4291.222us 3 3 100.00
chip_sw_rstmgr_cpu_info 0 3 0.00
chip_sw_rstmgr_cpu_info 324.970s 4437.316us 0 3 0.00
chip_sw_rstmgr_sw_req_reset 3 3 100.00
chip_sw_rstmgr_sw_req 313.820s 3470.099us 3 3 100.00
chip_sw_rstmgr_alert_info 3 3 100.00
chip_sw_rstmgr_alert_info 1483.230s 13911.120us 3 3 100.00
chip_sw_rstmgr_sw_rst 3 3 100.00
chip_sw_rstmgr_sw_rst 188.110s 3173.547us 3 3 100.00
chip_sw_rstmgr_escalation_reset 94 100 94.00
chip_sw_all_escalation_resets 626.340s 5801.425us 94 100 94.00
chip_sw_rstmgr_alert_handler_reset_enables 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 1364.390s 8015.324us 3 3 100.00
chip_sw_nmi_irq 3 3 100.00
chip_sw_rv_core_ibex_nmi_irq 601.310s 4877.042us 3 3 100.00
chip_sw_rv_core_ibex_rnd 3 3 100.00
chip_sw_rv_core_ibex_rnd 626.700s 4924.884us 3 3 100.00
chip_sw_rv_core_ibex_address_translation 3 3 100.00
chip_sw_rv_core_ibex_address_translation 208.310s 3486.719us 3 3 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 175.230s 2492.032us 3 3 100.00
chip_sw_rv_core_ibex_fault_dump 0 3 0.00
chip_sw_rstmgr_cpu_info 324.970s 4437.316us 0 3 0.00
chip_sw_rv_core_ibex_double_fault 0 3 0.00
chip_sw_rstmgr_cpu_info 324.970s 4437.316us 0 3 0.00
chip_jtag_csr_rw 3 3 100.00
chip_jtag_csr_rw 1026.700s 14129.370us 3 3 100.00
chip_jtag_mem_access 3 3 100.00
chip_jtag_mem_access 1113.580s 12835.252us 3 3 100.00
chip_rv_dm_ndm_reset_req 3 3 100.00
chip_rv_dm_ndm_reset_req 363.530s 4291.222us 3 3 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 3 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 218.110s 2580.177us 0 3 0.00
chip_rv_dm_access_after_wakeup 3 3 100.00
chip_sw_rv_dm_access_after_wakeup 309.460s 5939.128us 3 3 100.00
chip_sw_rv_dm_jtag_tap_sel 5 5 100.00
chip_tap_straps_rma 273.840s 4520.211us 5 5 100.00
chip_rv_dm_lc_disabled 0 3 0.00
chip_rv_dm_lc_disabled 194.800s 6008.722us 0 3 0.00
chip_sw_plic_all_irqs 9 9 100.00
chip_plic_all_irqs_0 706.370s 5958.537us 3 3 100.00
chip_plic_all_irqs_10 363.380s 3833.475us 3 3 100.00
chip_plic_all_irqs_20 390.220s 3714.893us 3 3 100.00
chip_sw_plic_sw_irq 3 3 100.00
chip_sw_plic_sw_irq 215.240s 2666.462us 3 3 100.00
chip_sw_timer 3 3 100.00
chip_sw_rv_timer_irq 189.380s 3370.796us 3 3 100.00
chip_sw_spi_device_flash_mode 3 3 100.00
rom_e2e_smoke 3615.290s 15486.838us 3 3 100.00
chip_sw_spi_device_pass_through 3 3 100.00
chip_sw_spi_device_pass_through 632.660s 6963.189us 3 3 100.00
chip_sw_spi_device_pass_through_collision 0 3 0.00
chip_sw_spi_device_pass_through_collision 267.370s 2887.673us 0 3 0.00
chip_sw_spi_device_tpm 3 3 100.00
chip_sw_spi_device_tpm 304.290s 3471.109us 3 3 100.00
chip_sw_spi_host_tx_rx 3 3 100.00
chip_sw_spi_host_tx_rx 243.360s 3424.154us 3 3 100.00
chip_sw_sram_scrambled_access 6 6 100.00
chip_sw_sram_ctrl_scrambled_access 502.090s 5491.270us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 518.510s 5774.451us 3 3 100.00
chip_sw_sleep_sram_ret_contents 6 6 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 638.050s 7234.549us 3 3 100.00
chip_sw_sleep_sram_ret_contents_scramble 495.890s 8462.313us 3 3 100.00
chip_sw_sram_execution 3 3 100.00
chip_sw_sram_ctrl_execution_main 551.610s 8311.839us 3 3 100.00
chip_sw_sram_lc_escalation 100 106 94.34
chip_sw_all_escalation_resets 626.340s 5801.425us 94 100 94.00
chip_sw_data_integrity_escalation 601.800s 5978.642us 6 6 100.00
chip_sw_sysrst_ctrl_reset 5 6 83.33
chip_sw_pwrmgr_sysrst_ctrl_reset 978.890s 8235.642us 3 3 100.00
chip_sw_sysrst_ctrl_reset 1373.210s 24169.989us 2 3 66.67
chip_sw_sysrst_ctrl_inputs 3 3 100.00
chip_sw_sysrst_ctrl_inputs 214.520s 2267.497us 3 3 100.00
chip_sw_sysrst_ctrl_outputs 3 3 100.00
chip_sw_sysrst_ctrl_outputs 248.430s 4095.877us 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 404.150s 4029.515us 3 3 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 2 3 66.67
chip_sw_sysrst_ctrl_reset 1373.210s 24169.989us 2 3 66.67
chip_sw_sysrst_ctrl_sleep_reset 2 3 66.67
chip_sw_sysrst_ctrl_reset 1373.210s 24169.989us 2 3 66.67
chip_sw_sysrst_ctrl_ec_rst_l 2 3 66.67
chip_sw_sysrst_ctrl_ec_rst_l 2980.250s 20332.659us 2 3 66.67
chip_sw_sysrst_ctrl_flash_wp_l 2 3 66.67
chip_sw_sysrst_ctrl_ec_rst_l 2980.250s 20332.659us 2 3 66.67
chip_sw_sysrst_ctrl_ulp_z3_wakeup 3 6 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 353.810s 6216.276us 3 3 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0.000s 0.000us 0 3 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 191.220s 3345.932us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 186.260s 2828.365us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 290.770s 3911.162us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 313.510s 3556.169us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1339.200s 7932.543us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 6667.050s 31594.763us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 2144.760s 12016.043us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 202.190s 2503.797us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 3 3 100.00
chip_sw_aes_masking_off 229.990s 3017.828us 3 3 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 3 33.33
chip_sw_rv_core_ibex_lockstep_glitch 142.260s 2797.182us 1 3 33.33
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 16542.830s 72035.502us 1 1 100.00
chip_sw_power_max_load 3 3 100.00
chip_sw_power_virus 1274.060s 6935.264us 3 3 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 511.680s 6548.849us 0 1 0.00
rom_e2e_jtag_debug_dev 748.850s 14521.519us 0 1 0.00
rom_e2e_jtag_debug_rma 202.960s 4057.111us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 73.610s 1960.880us 0 1 0.00
rom_e2e_jtag_inject_dev 73.570s 2848.228us 0 1 0.00
rom_e2e_jtag_inject_rma 89.340s 2868.021us 0 1 0.00
rom_e2e_self_hash 0 3 0.00
rom_e2e_self_hash 16.421s 0.000us 0 3 0.00
chip_sw_clkmgr_jitter_cycle_measurements 3 3 100.00
chip_sw_clkmgr_jitter_frequency 727.760s 4872.665us 3 3 100.00
chip_sw_edn_boot_mode 3 3 100.00
chip_sw_edn_boot_mode 365.970s 3195.259us 3 3 100.00
chip_sw_edn_auto_mode 3 3 100.00
chip_sw_edn_auto_mode 1263.250s 6824.454us 3 3 100.00
chip_sw_edn_sw_mode 3 3 100.00
chip_sw_edn_sw_mode 1520.720s 9182.578us 3 3 100.00
chip_sw_edn_kat 3 3 100.00
chip_sw_edn_kat 267.060s 2470.281us 3 3 100.00
chip_sw_flash_memory_protection 3 3 100.00
chip_sw_flash_ctrl_mem_protection 673.210s 5398.234us 3 3 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 3 3 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 200.900s 2431.007us 3 3 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 193.270s 2937.611us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 3 3 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 399.660s 5291.869us 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 393.150s 5081.570us 3 3 100.00
chip_sw_all_resets 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 1075.680s 11199.907us 3 3 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 511.680s 6548.849us 0 1 0.00
rom_e2e_jtag_debug_dev 748.850s 14521.519us 0 1 0.00
rom_e2e_jtag_debug_rma 202.960s 4057.111us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 3 3 100.00
chip_sw_rv_dm_access_after_escalation_reset 393.610s 5354.688us 3 3 100.00
chip_sw_plic_alerts 94 100 94.00
chip_sw_all_escalation_resets 626.340s 5801.425us 94 100 94.00
tick_configuration 0 3 0.00
chip_sw_rv_timer_systick_test 0.000s 0.000us 0 3 0.00
counter_wrap 0 3 0.00
chip_sw_rv_timer_systick_test 0.000s 0.000us 0 3 0.00
chip_sw_spi_device_output_when_disabled_or_sleeping 3 3 100.00
chip_sw_spi_device_pinmux_sleep_retention 204.370s 3526.561us 3 3 100.00
chip_sw_uart_watermarks 5 5 100.00
chip_sw_uart_tx_rx 483.760s 4344.000us 5 5 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3722.160s 18666.712us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 17 22 77.27
chip_sival_flash_info_access 200.120s 3434.987us 3 3 100.00
chip_sw_rstmgr_rst_cnsty_escalation 568.010s 5949.570us 3 3 100.00
chip_sw_otp_ctrl_rot_auth_config 107.880s 2982.418us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 194.290s 3498.320us 3 3 100.00
chip_sw_otp_ctrl_descrambling 237.160s 3620.057us 3 3 100.00
chip_sw_pwrmgr_lowpower_cancel 300.430s 3744.263us 2 3 66.67
chip_sw_pwrmgr_sleep_wake_5_bug 12.840s 0.000us 0 3 0.00
chip_sw_flash_ctrl_write_clear 274.490s 3689.921us 3 3 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*]
chip_sw_sleep_pin_mio_dio_val 114793357979058274144132628981972479749841642228071967533191367617427810801142 734
UVM_ERROR @ 2766.426500 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
UVM_INFO @ 2766.426500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch
chip_sw_spi_device_pass_through_collision 79297939430974137596207834013447775516270488477695787749933084458161128856060 593
UVM_ERROR @ 3165.077664 us: (chip_sw_spi_passthrough_collision_vseq.sv:183) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_collision_vseq] Compare mismatch
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 87052768673032515251230340070711435934894659363161357849937901924100371734838 621
UVM_ERROR @ 6440.012920 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 6440.012920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 94197763149211775298999313977474988030147531591522589739011962044126797223209 419
UVM_ERROR @ 5078.989709 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 5078.989709 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 71940483916986125373107288311616957563973072338895121143376578603433856321896 426
UVM_ERROR @ 7138.266878 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 7138.266878 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 65627566509550464314773531792683087739844327457496088552489713458571359610449 579
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2937.610872 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2937.610872 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 75947023657704276602543703617722023127600881904667898623034771807676142011578 408
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3285.957632 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3285.957632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 10936168909100467971552455713844504631961790525517785665445985481932529316631 391
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3482.069436 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3482.069436 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 53777963799696674627364652744790288379073626220908054260916215213107003630457 403
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3038.705820 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3038.705820 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access
chip_sw_otp_ctrl_rot_auth_config 98925534594566701969700925687699477126376526056035684534631436304981630343596 603
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 61295848990348539571855018888431559626632850524471312340985021554097758009918 407
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 15727874912922797802713222545869821862101020337752446160717724192262432566119 535
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 3920075097307687711001919057828304120895549806036647592486917041420584379303 475
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 51972055921812120116363212505291000295055606179235021322578595830820791412684 562
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 66966535801794357936979756162250308727477548617659067519671286982543372886295 548
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 2666941277474897807953081146627375063741666955824012471355984955908732020392 406
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 33578920179921919107760683406515713415542386116860017245607350721633360597430 406
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@77855) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_sw_rstmgr_cpu_info 12740340490456529446616001634685432108609165211799874583469467111771503171296 422
UVM_ERROR @ 3833.012390 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@77855) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 3833.012390 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_random_sleep_all_reset_reqs 99900935053677815131430388684877864397895743303202886267644339855697836881785 422
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 4915.810500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 4915.810500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 77542307217988917394984030984352826063220576665405867652367311663721177603930 428
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 7187.248500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7187.248500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 112610652079196572718334931898465075550587772324748151132709602110679771220010 435
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 12957.842000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 12957.842000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 9925037792805125233042101972901649333016816639985017562563609057099800837886 421
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 10695.492000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 10695.492000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 13800426902784421021518591843874304214049774605458268491008616154809267271448 393
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 5143.659000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5143.659000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 31222592918183426640795789443452149742148305396058124349652486411586519143779 409
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 6912.786000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6912.786000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 15364913673116614376813139234489200159206464020031398160398575925254882057596 455
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 23451.632500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 23451.632500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sysrst_ctrl_reset 96820316396855001121472684308175090766845293762628886670468786730409717705019 411
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 23220.580000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 23220.580000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 90216221132961382218621799518836594125895865461213629803569381324693359791175 421
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 10978.866500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 10978.866500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 101910243303197546981873825665882704502443292153441199556270522028753651237807 395
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 6109.675000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6109.675000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 23812662842645145815429408196005075099564001715705149864660371324794632590572 397
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 7771.300000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7771.300000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
chip_sw_rv_timer_systick_test 33180542616528717088069276148411486427649643661626373161820518028439756911253 None
Job timed out after 120 minutes
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 67119804946724544108780933567827058024397942076160110242643894024851014560155 None
Job timed out after 60 minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 99112228224574499035505202017080557315700707778397020921621289663265211914863 None
Job timed out after 240 minutes
chip_sw_rv_timer_systick_test 105472563649248800979013414082184713430545358951904788189414453819070870228779 None
Job timed out after 120 minutes
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 74000135231169827261804364874062749550877431867198084071612048488264905521143 None
Job timed out after 60 minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 33626128533990587375674972513245409171842311219524553127568254493446833938666 None
Job timed out after 240 minutes
chip_sw_rv_timer_systick_test 8162771656762039053292863353802159689444198554818695868135126663454084104515 None
Job timed out after 120 minutes
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 85332976874085972102400954525762765114565644071345841724825117155265135675913 None
Job timed out after 60 minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 82595897759330038516807340800769212859964654239570362357540616968962469837928 None
Job timed out after 240 minutes
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!
chip_sw_alert_test 77317411856472736816638437167967564801611098835264554884611398611155807911560 387
UVM_ERROR @ 2709.643216 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 43!
UVM_INFO @ 2709.643216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_test 94347927645535697629618753825198877815682436273047817101933209183965936494157 386
UVM_ERROR @ 2999.470312 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
UVM_INFO @ 2999.470312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 47752785591805423900739622952955506830824391531475768773620774030067145133883 387
UVM_ERROR @ 2920.226091 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2920.226091 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 77130884034712961509258536847634092731198794609180190424844791475625616721239 388
UVM_ERROR @ 2121.014692 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2121.014692 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 31316727925953088685841099827976727407100997050833933637266555873391362214342 387
UVM_ERROR @ 2990.834736 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2990.834736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 18876722868260068292251124507248484121634060552799288611076228955731947864157 390
UVM_ERROR @ 2241.444665 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2241.444665 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 58561157254948154669320163698317743885088148475184382703683715557285038827134 391
UVM_ERROR @ 2564.398488 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2564.398488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 34598980683642349164714397899242469686013258843899835710756808586008741679237 387
UVM_ERROR @ 2988.477337 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2988.477337 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 58259302685978650994549430616986661890318663427575233370378391573509145142640 387
UVM_ERROR @ 2617.338986 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2617.338986 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 40928834434683900590436437833317790845222731145457417367382923335111754381512 385
UVM_ERROR @ 2761.623990 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2761.623990 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 57260871003588906699040902531849813212507045781377446001688578045395989893244 384
UVM_ERROR @ 2987.350756 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2987.350756 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 75279606008401231411188826974632439853957606956015493094557109546019389416435 387
UVM_ERROR @ 2042.638888 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2042.638888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 73646466363394767474697181461186653807378454847635882058481570306234255462163 387
UVM_ERROR @ 3192.087365 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3192.087365 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 9691334438281274313863468034813436010690377354336771685409968817176959225528 386
UVM_ERROR @ 2619.094890 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2619.094890 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 12379476733629305026588823549475162667927413834171004416484612206986314446910 387
UVM_ERROR @ 3166.989215 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3166.989215 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 51385292837844151755000387980919329024382443937716982748794771429753696028045 394
UVM_ERROR @ 2817.152880 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2817.152880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 24372768399765613408552886133180361345148182377062232489530610495348954730911 387
UVM_ERROR @ 2506.623440 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2506.623440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 107963641910857343280447209869132936022603428036883368826924162612150698105763 386
UVM_ERROR @ 2685.538638 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2685.538638 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 2539602057901130237988866358104507996042889439044679149581496917097665319039 386
UVM_ERROR @ 2629.711907 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2629.711907 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 70677785416749157631753140428187906417788870025046435449913112719480901329875 387
UVM_ERROR @ 2499.128824 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2499.128824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 83822189526796113407301005132911833153556918268903223255365412506910758288284 389
UVM_ERROR @ 2542.769020 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2542.769020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 68604187462701486575090031195829053989770946331064369280724885515665633261214 387
UVM_ERROR @ 2932.355826 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2932.355826 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 88306564274167749459351842973179165177827782503985666404317583026144998751686 387
UVM_ERROR @ 2879.441908 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2879.441908 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 93819838002578124594253931370345422658577659675282172289157396127470569928957 406
UVM_ERROR @ 2706.363740 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2706.363740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 111971818633934296536397060805884340487920015466174283154643170498380440271807 397
UVM_ERROR @ 2447.682728 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2447.682728 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 95821147946759872480820284007933156253200982179177683055965914715236589550844 392
UVM_ERROR @ 2412.206055 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2412.206055 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 3143995730446091270401651229338469191129212642263885314222549344882370585746 387
UVM_ERROR @ 2699.251064 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2699.251064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 45419600022820512255445355663017797250743920674111049049862860760655755169247 390
UVM_ERROR @ 2345.361665 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2345.361665 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 22477648137990896771533926446745480765473647438202260671246966403332574982444 387
UVM_ERROR @ 3364.893140 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3364.893140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 79602915015588202206236596394672201704971053771882270435367670462221672852928 387
UVM_ERROR @ 2331.048628 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2331.048628 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 80470036759567386765912466410735660681546569188390671066692020055835185427791 387
UVM_ERROR @ 2428.429316 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2428.429316 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 19770512833482200513070758990933601642099506656210188705641496955197790690054 387
UVM_ERROR @ 2950.615914 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2950.615914 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 33654486879809982627492812927575367607036808379444120952038030984468258665862 387
UVM_ERROR @ 3095.394092 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3095.394092 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 31202797084030433163768782964473731120963998330481513942324005213483822842864 387
UVM_ERROR @ 3129.930225 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3129.930225 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 8700946873835901779373363515140096763516405870207312656974190636557067652755 387
UVM_ERROR @ 2506.080652 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2506.080652 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 73910372925516178896615673393290687651742106273117226124576229474545734583303 393
UVM_ERROR @ 1922.025080 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 1922.025080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 34542053098094614673998659916092986081052771473886203077935794392865031562559 388
UVM_ERROR @ 2744.337042 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2744.337042 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 23032878260995315146627012994330421235592188797565544347961883818988629546149 394
UVM_ERROR @ 2394.353536 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2394.353536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 84710486091658531304905465473524832450180799293323325418422897122901986093831 387
UVM_ERROR @ 2425.236982 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2425.236982 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 92791211248045676069832313597946632937376641931396650438271747800084436690855 391
UVM_ERROR @ 2700.341960 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2700.341960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 58211123122940465837187382842561095007664264434540113779114912140537294296113 393
UVM_ERROR @ 2921.116208 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2921.116208 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 50126368015787284274296637985578149001711184637742935610899904194386868786784 395
UVM_ERROR @ 2848.897678 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2848.897678 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 91216950720455937816950686942051145325237790405775389766539242661690125879745 387
UVM_ERROR @ 2828.039144 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2828.039144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 91834947853467044974564100379030535393130633958597569145355744495404494694798 391
UVM_ERROR @ 3002.347085 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3002.347085 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 82506350606548020161484252723434661451175441386157106413610458122422184461738 397
UVM_ERROR @ 2676.589636 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2676.589636 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 97909981109941339160471460287758714887905813185991475933082287821153731291482 387
UVM_ERROR @ 2328.020700 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2328.020700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 37982299236962814500308413729766493806712504528011562047369696547208023740273 389
UVM_ERROR @ 3478.639054 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3478.639054 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 79840938322865927149278390640507634434165119947525233688948631487532490390615 386
UVM_ERROR @ 2719.274038 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2719.274038 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 94299098640715351101216829863309945873172217528668440942979514117523647099564 394
UVM_ERROR @ 2306.045875 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2306.045875 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 27049394081889563993276576259287555007666682921427409469007248798771281007760 387
UVM_ERROR @ 3225.505815 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3225.505815 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 42184093660516827485696585596170511282792548862103535380077317286733369507695 392
UVM_ERROR @ 2737.970188 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2737.970188 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 29251037257474270738155486939468295819236350470914168233017017522485848524158 389
UVM_ERROR @ 2895.614248 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2895.614248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 65814207847072467366414942244200813866391082850320301723020505859084331270204 387
UVM_ERROR @ 2122.210330 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2122.210330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 66518280661982775959195889203857484013978356268969572219797506045709321520406 387
UVM_ERROR @ 2244.396360 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2244.396360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 45580032466853978454194389721944370710355608374008307996550458083583278277643 392
UVM_ERROR @ 2749.324346 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2749.324346 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 88746162526089719885083889432399194138175024560976380690906440297838803194815 387
UVM_ERROR @ 3484.060667 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3484.060667 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 61026934335768271485442462685566482683319596373670423570500459756713418733655 394
UVM_ERROR @ 2355.851456 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2355.851456 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 13265325532212165008739223605034633355955874377819851018232982507371296778284 402
UVM_ERROR @ 2525.654376 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2525.654376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 113308703537368067439247129830311001345966576528748607862764115023284289940700 395
UVM_ERROR @ 2930.458416 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2930.458416 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 158245730634370096958889890484664025053669815641312137356005022292315505975 389
UVM_ERROR @ 2979.396824 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2979.396824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 90459690526796086195420076392306656160616347082768640904992071590022971438549 387
UVM_ERROR @ 2611.365730 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2611.365730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 40523945417271515552336768671510103179446945883218046896160157686938405550518 387
UVM_ERROR @ 2879.057785 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2879.057785 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 55259556356540132651165834267507008108101815923696083105988790206291071932645 393
UVM_ERROR @ 2642.283700 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2642.283700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 77502097621694177581663845018992717482363757331585091305075104854725401401323 387
UVM_ERROR @ 2609.424269 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2609.424269 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 14676555716477138975240624726155658322578713738541544874210990738270970235293 389
UVM_ERROR @ 2024.633140 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2024.633140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 95277664260586871620670167767346039315328836700985116073183265305381900194484 390
UVM_ERROR @ 2573.906955 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2573.906955 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 109921165051590735612802534606222197187425274468014182668250197340744758313116 391
UVM_ERROR @ 2825.689080 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2825.689080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 73586480293314075221322411043350493470680981629242612769474759420153983737210 398
UVM_ERROR @ 3230.712020 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3230.712020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 97916879013173897523939264053079567240814539553632403131921969896476434672637 386
UVM_ERROR @ 3533.788007 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3533.788007 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 78440303076100675821147439776277748622777067819817084850211326535582025385175 386
UVM_ERROR @ 3364.096070 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3364.096070 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 97125689134324087887264986999931653316307343442557945111659872644295826601162 386
UVM_ERROR @ 2406.932158 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2406.932158 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 84507959560736347719698379310055123428700595217693656102113616603040929188475 386
UVM_ERROR @ 3171.890625 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3171.890625 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 7290184126945977760144965879761577760345985006966353880535117009439950842044 386
UVM_ERROR @ 2344.111566 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2344.111566 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 38966830984796003467060299266138193633517366668494016994878094984435938528411 389
UVM_ERROR @ 2825.314869 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2825.314869 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 67132623545839457881762026052168602403673283859380905965997822915407048832065 399
UVM_ERROR @ 2842.851720 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2842.851720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 105788105848198330852067476003394590076107232044118032775097511705408534779130 388
UVM_ERROR @ 2626.525308 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2626.525308 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 40900370344260167340418756081425881587487117671568709393916108728716736476299 397
UVM_ERROR @ 2868.529440 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2868.529440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 34429070317637085077709520381762370249076828860228659032492061476189906673962 389
UVM_ERROR @ 2286.713575 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2286.713575 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 63302871668053941909405320432396841246865234733818775246930705724477475521947 392
UVM_ERROR @ 2555.287070 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2555.287070 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 61550137276184182855035961680685399520197392255736249354258172229885054455526 391
UVM_ERROR @ 2727.872870 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2727.872870 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 62959000107223648838105049887541958168061199326339795665808160286342729139663 387
UVM_ERROR @ 2742.815846 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2742.815846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 106829767799774395520394392214401884663857272584047018201667223084693368189487 390
UVM_ERROR @ 2790.888520 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2790.888520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 7530213265775653445729515258409620461230339216946895154287884565549602288723 386
UVM_ERROR @ 3202.863760 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3202.863760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 17063962049067531660592992981493526057050410519678228113366724167946029645989 386
UVM_ERROR @ 3137.486536 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3137.486536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 81320143928756564091814836246327866672506391007404517604408424224542633181721 393
UVM_ERROR @ 2872.256488 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2872.256488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 78745754020925548378592209550526721431125540841733476081118553859689088960955 391
UVM_ERROR @ 2469.630045 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2469.630045 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 51618102438021718970952793753348079087753490247626066401360832623978360944563 393
UVM_ERROR @ 3041.744550 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3041.744550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 100560882161131492785611773626001906482563144881283413709588202698808958151257 410
UVM_ERROR @ 2660.045126 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2660.045126 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 109116297280356781945480583470620523591556774300844975386415221203951461047778 401
UVM_ERROR @ 2641.240135 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2641.240135 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 5939170998308494312388090473804401335068655278902719014012466316478669338554 396
UVM_ERROR @ 3167.631516 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3167.631516 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 62656624452612227070486950155524485875250181056013864986995716707152171712486 387
UVM_ERROR @ 3226.607760 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3226.607760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 32460672873799199067971984716151149327849554105913747817393783784954862091088 386
UVM_ERROR @ 3138.431538 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3138.431538 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status()
chip_sw_pwrmgr_lowpower_cancel 61742179945671882214729648925395980991646706033406575309320883789781649254912 393
UVM_ERROR @ 2768.930563 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
UVM_INFO @ 2768.930563 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
chip_sw_pwrmgr_sleep_wake_5_bug 31413612357950388606492539868659590758925179226041019400520393349469796189720 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
INFO: Elapsed time: 0.224s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
rom_e2e_self_hash 77315815541266979972804632169054588983931125586968430347296815431894466175730 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
INFO: Elapsed time: 4.147s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 39287354276389168954423525431470669955994941855612420267364844911366204356569 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
INFO: Elapsed time: 0.496s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
rom_e2e_self_hash 102260326775538565434201953854992255083549528723870737818315375275181428452347 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
INFO: Elapsed time: 0.755s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 74482915129699513105923329330472187605770275528575600638342682825649004104114 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
INFO: Elapsed time: 0.211s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
rom_e2e_self_hash 50350426169219397350815253595039234745263754507312887490348000160335794825469 None
Computing main repo mapping:
Loading:
Loading: 0 packages loaded
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
INFO: Elapsed time: 0.203s
INFO: 0 processes.
ERROR: Build did NOT complete successfully
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation.
chip_sw_rv_core_ibex_lockstep_glitch 71611560197327968024252313982291159951372221953370307565438719638278870814552 406
UVM_FATAL @ 2682.246460 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2682.246460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_core_ibex_lockstep_glitch 78342799028683588511135721003165840787039382297290887084793234069314813612248 393
UVM_FATAL @ 2287.561558 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2287.561558 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 101131252896310474192582822995329570085621152248484596685340316572498945481834 403
UVM_ERROR @ 3143.126000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3143.126000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_idle_load 21442111512517674045315616631270179226031355495133385839007376016395717023794 401
UVM_ERROR @ 3412.362500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3412.362500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_idle_load 106505651590843180245321440109212911854348702619187012833938859625486608171224 391
UVM_ERROR @ 2638.517500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 2638.517500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 82432193453587557504532884987336670989502391607361398979621860203901923346942 403
UVM_ERROR @ 3179.164000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3179.164000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 72656803616397280075730404314962749457833935440179899422342442779457824739231 404
UVM_ERROR @ 3692.876000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3692.876000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 101738295696132922908051269098251938563329781151041506084563014492701828694991 397
UVM_ERROR @ 3270.864500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3270.864500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
chip_sw_ast_clk_rst_inputs 95731115696220488358651773652599550559812107705590438965352310994130083827578 413
UVM_ERROR @ 16849.305529 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
UVM_INFO @ 16849.305529 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 111855560932567992626963895008914629032765997818190581503601477348054317394938 414
UVM_ERROR @ 18221.904716 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
UVM_INFO @ 18221.904716 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)'
rom_e2e_boot_policy_valid_a_good_b_good_dev 65927181350547854586977944500632811373640117317337806599468775002444253400992 593
Offending '(pend_req[h2d.a_source].pend == 0)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 2963193660ps failed at 2963193660ps
Offending '(pend_req[h2d.a_source].pend == 0)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 2963380476ps failed at 2963380476ps
Offending '(pend_req[h2d.a_source].pend == 0)'
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 81275385421042428013930286011103170938413820600117015584248288974131220185687 579
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 56048383621030634443218258738553617054616046537906307472989651291970716865402 614
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 95165610916852367453339076559239555228564748764099159388228961053178761605822 598
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 82738542056028104753493705047310881894053103636562613692633311358240189430521 586
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 51618562407031549015522929766979174071830134060405403768554107839997806800137 640
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 40009246438119019569693527174310087525466414320415295806719253516333064313363 637
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 33128616290227519701656646603171807249915847886557192761784467244562324194430 634
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 51734013177935909321677674552761562415880623807620251843024164674473643004108 591
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 91010810635844900417449605504518230066270610268330482935045606293367308447523 546
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 72970987905357807712208197537740404207860866129826776178565241039080862406305 650
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod 41522579836736396621154503866927329989248867761602016019299703400820471719366 719
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 70732259540454310445262148604887135383497613367590098020378294235248426220063 683
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 88969852645399041846992732334950012671572258174768367261545954025202586697947 679
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 56038293817288963579738382273879468350409412003285841440642177400425126204376 675
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 94143115149803593674171756112249592037464706644403312454003636758491028408024 539
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 28140698619241422102858534560491338306268031051361987246217546075957873335359 596
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 64114790930386508645032479575915171260214378812632237869226750777336261130559 693
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 33794980493671135328110131764278864756824902748626140608028612960195226861371 566
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 74480171695098204468500786680559525055591290077678479597386189442305994808180 626
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 114622253427343964789108427545861753911175638604654132552929587122438313969899 624
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 97070930603758045966704810863179391572898837469536217319906442828621638541030 701
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 68883316611266927600407421783851748179705428461868401735687267143055548302970 642
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 34460395921243516697542144766312681205492344833229710097594497605791313500608 713
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 100569317764160400076205775719238112149861690225692119360556064204865663175562 613
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 39315955660296509999527061375968437961384693429402630890050357428451278770299 653
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
rom_e2e_jtag_debug_dev 43974747736965657401306611213625373673570226949793577934606213113075978525309 507
UVM_FATAL @ 14521.519144 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
UVM_INFO @ 14521.519144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:613) [debugger] Check failed dcsr.cause == exp_debug_cause (* [*] vs * [*])
rom_e2e_jtag_debug_rma 95687833695457942378320329502154645387263004689762330645505475191215300882875 552
UVM_ERROR @ 4057.110822 us: (jtag_rv_debugger.sv:613) [debugger] Check failed dcsr.cause == exp_debug_cause (0 [0x0] vs 2 [0x2])
UVM_INFO @ 4057.110822 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_meas 19443451243890363161756730945468485687519777654649734137049806752651922084709 537
UVM_ERROR @ 16784.044500 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 16784.044500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_no_meas 51206167824895720670200840217543970044026783353040995122099434648470839240265 534
UVM_ERROR @ 17195.838491 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 17195.838491 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_invalid_meas 113319069145174551916960557868891075114062698893368052901679085820861077963412 480
UVM_ERROR @ 15834.041647 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 15834.041647 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
rom_raw_unlock 72887517418644509163157069671284445888890441130038690670714865343738057184565 468
UVM_FATAL @ 15856.881056 us: (chip_sw_lc_raw_unlock_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
UVM_INFO @ 15856.881056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_raw_unlock 23724380643857912956230692409178195103865990471657988712035947092952837545261 440
UVM_FATAL @ 15204.844510 us: (chip_sw_lc_raw_unlock_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
UVM_INFO @ 15204.844510 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 1392981930532124681354829756571543630645992940620206630162126242173478269938 408
Offending '$stable(key_data_i)'
UVM_ERROR @ 5190.755180 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5190.755180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_keymgr_functest 55193500217508816449566736492538831700969569819420814381295138477319336093834 405
Offending '$stable(key_data_i)'
UVM_ERROR @ 5257.168344 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5257.168344 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_keymgr_functest 102263028824733057933896221368802629417419955654258309785287009933124370035690 407
Offending '$stable(key_data_i)'
UVM_ERROR @ 5000.440509 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5000.440509 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 16387783492314029008980445786046869688064108582391649295489843098762041323164 399
UVM_ERROR @ 3146.132765 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 3146.132765 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pass_through_collision 83081628125281035405771148074052175217182005643845113709143953792737243316558 401
UVM_ERROR @ 2887.673304 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 2887.673304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@106311) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_sw_rstmgr_cpu_info 76150869645664138973950752705254526462524583949383630962588482381625280009299 414
UVM_ERROR @ 4437.316428 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@106311) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 4437.316428 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
chip_sw_sysrst_ctrl_ec_rst_l 46234527184886455735763910279312751376690630526552879055735961076801178540872 399
UVM_ERROR @ 11727.047932 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
UVM_INFO @ 11727.047932 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_hmac_oneshot 100543067990435788427511544542313526133681326908677092111430527887014627052697 404
UVM_ERROR @ 12018.701078 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
UVM_INFO @ 12018.701078 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(reset_cause == HwReq)'
chip_sw_sensor_ctrl_alert 76279021195350233314690275439187805396043975769235279431153774212219237506359 395
Offending '(reset_cause == HwReq)'
UVM_ERROR @ 2106.173430 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
UVM_INFO @ 2106.173430 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78207) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_sw_rstmgr_cpu_info 85318926189977140562248057050851430233133818456335437173949449070613667731520 411
UVM_ERROR @ 3957.673900 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78207) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h1 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 3957.673900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *!
chip_sw_alert_test 19764788186594310543310741399621710082598137625751629020079239390753146744098 386
UVM_ERROR @ 2903.875680 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 28!
UVM_INFO @ 2903.875680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:905) virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
chip_sw_all_escalation_resets 112767858630849123747195329572728160534155370215696718570402064593584446119352 399
UVM_ERROR @ 2263.526488 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
UVM_INFO @ 2263.526488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 71535513224052449728318992566638108186315558016827042578201992670004853210809 395
UVM_ERROR @ 3133.405188 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
UVM_INFO @ 3133.405188 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 75294972921112603687634665233165830370799536135656726588869896345848885727297 409
UVM_ERROR @ 2780.263362 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
UVM_INFO @ 2780.263362 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 108529087991939721077436112698331005248071693620254352392765287686088981322009 401
UVM_ERROR @ 2667.519348 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
UVM_INFO @ 2667.519348 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got *
chip_sw_all_escalation_resets 79723674801936328306420627451474400783454486417732186366119547333514726895423 399
UVM_ERROR @ 3116.057554 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3116.057554 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@40483) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 88871885708951906392532528606363272423388416058785567552260969413794050234884 214
UVM_ERROR @ 2766.376732 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@40483) { a_addr: 'h10498 a_data: 'h150cca99 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3 a_opcode: 'h4 a_user: 'h1954d d_param: 'h0 d_source: 'h3 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2766.376732 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 44269728152095025820619119490107298445940264126642088348886308517550333298587 223
UVM_ERROR @ 3528.325775 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x105a8 read out mismatch
UVM_INFO @ 3528.325775 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_rv_dm_lc_disabled 49519008158182482066915556116902423164050155740073682271292133455946101841381 232
UVM_ERROR @ 6008.721777 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x1043c read out mismatch
UVM_INFO @ 6008.721777 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_rv_dm_lc_disabled 28618017480823216069457618681590558026710827585378638461220116391322034652745 212
UVM_ERROR @ 2470.157400 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x104c8 read out mismatch
UVM_INFO @ 2470.157400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@212911) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 47351310250973186484029000193223553655816260982735412982688539864030034991657 239
UVM_ERROR @ 5748.945970 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@212911) { a_addr: 'h107a4 a_data: 'h53e0a0af a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h32 a_opcode: 'h4 a_user: 'h1bd72 d_param: 'h0 d_source: 'h32 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 5748.945970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37601) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 8089435633351674660674437871677076414041746937061776160223960971407533420214 214
UVM_ERROR @ 2867.999882 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37601) { a_addr: 'h107b0 a_data: 'h958b1df a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4 a_opcode: 'h4 a_user: 'h19532 d_param: 'h0 d_source: 'h4 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2867.999882 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31623) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 20111029179170549203155640944567203324801861795094077256215207969834277843021 214
UVM_ERROR @ 1679.561154 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31623) { a_addr: 'h10630 a_data: 'hb8cdedc8 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h15 a_opcode: 'h4 a_user: 'h1a2a9 d_param: 'h0 d_source: 'h15 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1679.561154 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31659) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 3396211189794093099969604746795023839302686219848537942040217735627814994505 221
UVM_ERROR @ 1901.929005 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31659) { a_addr: 'h10558 a_data: 'h560a692d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h34 a_opcode: 'h4 a_user: 'h18a23 d_param: 'h0 d_source: 'h34 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1901.929005 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31455) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 62765185604923074642312016487756133044291947902672083187221591322252722168918 214
UVM_ERROR @ 2178.556248 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31455) { a_addr: 'h106b8 a_data: 'h676162a4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h17 a_opcode: 'h4 a_user: 'h186b2 d_param: 'h0 d_source: 'h17 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2178.556248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32171) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 106869695525501244815202867450206110834999752839630186851274682425865994043498 221
UVM_ERROR @ 2459.938896 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32171) { a_addr: 'h10450 a_data: 'h4f47cf5a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1e a_opcode: 'h4 a_user: 'h19986 d_param: 'h0 d_source: 'h1e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2459.938896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@43511) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 115598904617521959187346211862584496574518027389916843458542704117498254457385 214
UVM_ERROR @ 2533.522700 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@43511) { a_addr: 'h1079c a_data: 'h4a92b162 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1a a_opcode: 'h4 a_user: 'h195fb d_param: 'h0 d_source: 'h1a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2533.522700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32209) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 98111414498642448941295242755964881031841945216837682310599566975264202797408 221
UVM_ERROR @ 1673.958166 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32209) { a_addr: 'h1067c a_data: 'he3184bce a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h21 a_opcode: 'h4 a_user: 'h19267 d_param: 'h0 d_source: 'h21 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1673.958166 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32797) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 51249715304471378755522166620630135487984842444657057839242406933166015330796 214
UVM_ERROR @ 2712.426750 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32797) { a_addr: 'h10668 a_data: 'hd3b28fe2 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h35 a_opcode: 'h4 a_user: 'h1ba73 d_param: 'h0 d_source: 'h35 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2712.426750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37199) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 27091443371932985440374048037673927405073983396510888978865693704649130420720 223
UVM_ERROR @ 2218.054200 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37199) { a_addr: 'h1140 a_data: 'hf8742b41 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h32 a_opcode: 'h1 a_user: 'h24e00 d_param: 'h0 d_source: 'h32 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2218.054200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32719) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 45716827502249491548527450523911156399850278170170791015290873417559209268863 214
UVM_ERROR @ 2433.405744 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32719) { a_addr: 'h107d8 a_data: 'ha13906fe a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h6 a_opcode: 'h4 a_user: 'h1b196 d_param: 'h0 d_source: 'h6 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2433.405744 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32149) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 86527458076940577617044672812633273887867331134223927299307736404411015143586 221
UVM_ERROR @ 2845.628135 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32149) { a_addr: 'h10728 a_data: 'h1bd90f85 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h17 a_opcode: 'h4 a_user: 'h1958e d_param: 'h0 d_source: 'h17 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2845.628135 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37449) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 13394340472350348141489619595897044369061308654775913479130013464643365336691 214
UVM_ERROR @ 2354.744360 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37449) { a_addr: 'h10660 a_data: 'h595d508 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3 a_opcode: 'h4 a_user: 'h1aeee d_param: 'h0 d_source: 'h3 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2354.744360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31737) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 29232529873706480326914656947913220484874051258894426508804216412666440769992 221
UVM_ERROR @ 2487.352067 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31737) { a_addr: 'h107f8 a_data: 'h63cac9c6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h8 a_opcode: 'h4 a_user: 'h1a931 d_param: 'h0 d_source: 'h8 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2487.352067 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34565) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 28921914344868009505959810888390258736797198721049761660671148048448624821297 214
UVM_ERROR @ 2615.870952 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34565) { a_addr: 'h107c0 a_data: 'h722ae7b7 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h38 a_opcode: 'h4 a_user: 'h181ea d_param: 'h0 d_source: 'h38 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2615.870952 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31697) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 33717347206579734289879183439359917771699925869069801407042767215852838994319 221
UVM_ERROR @ 2433.829210 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31697) { a_addr: 'h104d4 a_data: 'h2c85a7ac a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2c a_opcode: 'h4 a_user: 'h1a5c7 d_param: 'h0 d_source: 'h2c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2433.829210 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38385) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 23577824276684256474041431887299804673637670475801134839466121588814870238852 214
UVM_ERROR @ 2893.395960 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38385) { a_addr: 'h10418 a_data: 'hce3dc8fd a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h8 a_opcode: 'h4 a_user: 'h1a5ac d_param: 'h0 d_source: 'h8 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2893.395960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@214075) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 76045101932075214336748427935004640963540285133257813994051421362145564755427 239
UVM_ERROR @ 7364.870640 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@214075) { a_addr: 'h10674 a_data: 'h5da8e138 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h23 a_opcode: 'h4 a_user: 'h186a1 d_param: 'h0 d_source: 'h23 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 7364.870640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34645) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 96018096840766592556058705856492109597630039792235671684099572443942178277316 214
UVM_ERROR @ 2208.764216 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34645) { a_addr: 'h10560 a_data: 'h3b9e5fc3 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3e a_opcode: 'h4 a_user: 'h1a2c3 d_param: 'h0 d_source: 'h3e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2208.764216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@39299) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 64975464908390166322976493046815845106960037695629768286967006797357970689076 214
UVM_ERROR @ 2942.165823 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@39299) { a_addr: 'h1079c a_data: 'h9e9b4ec0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3c a_opcode: 'h4 a_user: 'h195d7 d_param: 'h0 d_source: 'h3c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2942.165823 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32445) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 56371420188259364768769164334594766353817077501981020190295663639651736968916 214
UVM_ERROR @ 2220.703980 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32445) { a_addr: 'h104c8 a_data: 'had0ad06b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3c a_opcode: 'h4 a_user: 'h19969 d_param: 'h0 d_source: 'h3c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2220.703980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31851) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 39117207272266192083172570140343682838682042990795219908210171231454332040106 221
UVM_ERROR @ 2949.442180 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31851) { a_addr: 'h1033c a_data: 'hdb1323f2 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h26 a_opcode: 'h4 a_user: 'h1aed9 d_param: 'h0 d_source: 'h26 d_data: 'h517 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd10 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2949.442180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32827) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 74830420516400812532623331131136268948118479307170161174969892739156132273031 214
UVM_ERROR @ 2316.299165 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32827) { a_addr: 'h10538 a_data: 'ha3e5c90a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1a a_opcode: 'h4 a_user: 'h1ba5c d_param: 'h0 d_source: 'h1a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2316.299165 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32191) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 791694671929575070085603423591631225063726366425038216865079094627395278293 214
UVM_ERROR @ 2444.627503 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32191) { a_addr: 'h105b8 a_data: 'he3191461 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h37 a_opcode: 'h4 a_user: 'h18aba d_param: 'h0 d_source: 'h37 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2444.627503 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32197) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 24113745759077403374929278083573981866306194911970310442207671249858338048525 221
UVM_ERROR @ 2643.481392 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32197) { a_addr: 'h10658 a_data: 'h5568a14e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hc a_opcode: 'h4 a_user: 'h18679 d_param: 'h0 d_source: 'hc d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2643.481392 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31847) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 45705498966079157233254089176165972794917467210020412038182127010000072386855 214
UVM_ERROR @ 1855.783063 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31847) { a_addr: 'h10500 a_data: 'h7aeb4e7b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3e a_opcode: 'h4 a_user: 'h1929b d_param: 'h0 d_source: 'h3e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1855.783063 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33719) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 12858459543446978741698516839457213317613939883116664104046352297279173133387 214
UVM_ERROR @ 2846.207338 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33719) { a_addr: 'h10418 a_data: 'he7e62e2b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3c a_opcode: 'h4 a_user: 'h1a598 d_param: 'h0 d_source: 'h3c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2846.207338 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31937) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 14516779687172853036124813958239704419785227955528168647621954103993211858487 221
UVM_ERROR @ 2338.850345 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31937) { a_addr: 'h10548 a_data: 'hf1f2230b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1d a_opcode: 'h4 a_user: 'h1ae95 d_param: 'h0 d_source: 'h1d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2338.850345 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33285) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 78461629973081572523330677009115592672628406604069460756227119035946585528518 214
UVM_ERROR @ 2677.817704 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33285) { a_addr: 'h104d8 a_data: 'h6068553d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3f a_opcode: 'h4 a_user: 'h1bdbb d_param: 'h0 d_source: 'h3f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2677.817704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@213387) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_csr_mem_rw_with_rand_reset 5515517139153444603859376045536181913776918908941623630911582045062218963319 239
UVM_ERROR @ 5092.493395 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@213387) { a_addr: 'h105a0 a_data: 'ha6ab51df a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h35 a_opcode: 'h4 a_user: 'h1baf4 d_param: 'h0 d_source: 'h35 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 5092.493395 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@39561) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 95736538932458280228583351033803595857828080875147054195150587339330647325182 214
UVM_ERROR @ 2271.584692 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@39561) { a_addr: 'h10768 a_data: 'h2951a3ce a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h39 a_opcode: 'h4 a_user: 'h1bd4b d_param: 'h0 d_source: 'h39 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2271.584692 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32165) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 80126598022100835104725837078446598608055783556404323707858597312180590436317 214
UVM_ERROR @ 2422.123616 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32165) { a_addr: 'h10410 a_data: 'h32d4aacb a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h6 a_opcode: 'h4 a_user: 'h1b167 d_param: 'h0 d_source: 'h6 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2422.123616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32407) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 27617767174456986402735104709744669660219450510960826856943573785563093612228 214
UVM_ERROR @ 2043.115790 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32407) { a_addr: 'h107f0 a_data: 'h8f1c2d0e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h14 a_opcode: 'h4 a_user: 'h1bdf2 d_param: 'h0 d_source: 'h14 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2043.115790 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32447) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 3649422115862331882316430608915539268035170409765556185998291583531637563715 214
UVM_ERROR @ 2406.254520 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32447) { a_addr: 'h10420 a_data: 'h6764de3 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h17 a_opcode: 'h4 a_user: 'h18d5b d_param: 'h0 d_source: 'h17 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2406.254520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31751) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 40872775597677220478432005724852944810694591146311385412277610925105272784319 214
UVM_ERROR @ 2041.375647 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31751) { a_addr: 'h106b0 a_data: 'h3b648a85 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h19249 d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2041.375647 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38559) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 104073034443637244428618164681898608076196543071379738625976896497845179136533 214
UVM_ERROR @ 1869.122295 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38559) { a_addr: 'h106d8 a_data: 'heb7b435c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h29 a_opcode: 'h4 a_user: 'h1b6e3 d_param: 'h0 d_source: 'h29 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1869.122295 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32179) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 26461241726326176548753255875063217145684376823934721161200468090074958498116 214
UVM_ERROR @ 2328.162120 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32179) { a_addr: 'h10358 a_data: 'heaa4a982 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3d a_opcode: 'h4 a_user: 'h19249 d_param: 'h0 d_source: 'h3d d_data: 'h7b302573 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd1f a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2328.162120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33673) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 22623565885910973552169914534101746826807873768515302478861953401946280985663 214
UVM_ERROR @ 1782.496966 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33673) { a_addr: 'h10748 a_data: 'hfde53998 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h29 a_opcode: 'h4 a_user: 'h1a5df d_param: 'h0 d_source: 'h29 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1782.496966 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32649) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 80813382140566564206159275827031353564586381644415842309644883696671916133223 214
UVM_ERROR @ 2782.747630 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32649) { a_addr: 'h1058c a_data: 'hd4f9df92 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h37 a_opcode: 'h4 a_user: 'h1ba32 d_param: 'h0 d_source: 'h37 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2782.747630 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31735) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 70588596302168260855206411123339043339914363036233129397958292546890970645523 214
UVM_ERROR @ 2836.553336 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31735) { a_addr: 'h1076c a_data: 'h9bc729ea a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h32 a_opcode: 'h4 a_user: 'h1b1f5 d_param: 'h0 d_source: 'h32 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2836.553336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36601) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
chip_tl_errors 75270094864132182224202221717965279821674099947150893181135670387947370049472 214
UVM_ERROR @ 2120.280100 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36601) { a_addr: 'h1067c a_data: 'h1e7cf69e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3c a_opcode: 'h4 a_user: 'h19220 d_param: 'h0 d_source: 'h3c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 2120.280100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---