clkmgr Simulation Results

Simulation Results: clkmgr

18/01/2026 00:06:04 sha: 8ead910 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
94.41 %

code
98.95 %

assert
96.47 %

func
87.82 %

line
99.34 %

branch
99.17 %

cond
96.26 %

toggle
100.00 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		97.95%
V3		100.00%

130/130 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	clkmgr_smoke	1.650s	282.729us	50	50	100.00
csr_hw_reset				5	5	100.00
	clkmgr_csr_hw_reset	1.250s	101.396us	5	5	100.00
csr_rw				20	20	100.00
	clkmgr_csr_rw	1.410s	115.074us	20	20	100.00
csr_bit_bash				5	5	100.00
	clkmgr_csr_bit_bash	6.320s	479.096us	5	5	100.00
csr_aliasing				5	5	100.00
	clkmgr_csr_aliasing	2.440s	122.726us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	clkmgr_csr_mem_rw_with_rand_reset	1.960s	40.831us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	clkmgr_csr_rw	1.410s	115.074us	20	20	100.00
	clkmgr_csr_aliasing	2.440s	122.726us	5	5	100.00

640/640 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				50	50	100.00
	clkmgr_peri	1.610s	148.487us	50	50	100.00
trans_enables				50	50	100.00
	clkmgr_trans	1.910s	162.571us	50	50	100.00
extclk				50	50	100.00
	clkmgr_extclk	2.210s	282.206us	50	50	100.00
clk_status				50	50	100.00
	clkmgr_clk_status	1.290s	88.138us	50	50	100.00
jitter				50	50	100.00
	clkmgr_smoke	1.650s	282.729us	50	50	100.00
frequency				50	50	100.00
	clkmgr_frequency	23.190s	2472.810us	50	50	100.00
frequency_timeout				50	50	100.00
	clkmgr_frequency_timeout	17.150s	2174.206us	50	50	100.00
frequency_overflow				50	50	100.00
	clkmgr_frequency	23.190s	2472.810us	50	50	100.00
stress_all				50	50	100.00
	clkmgr_stress_all	51.590s	8220.655us	50	50	100.00
alert_test				50	50	100.00
	clkmgr_alert_test	1.790s	204.377us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	clkmgr_tl_errors	6.940s	1486.867us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	clkmgr_tl_errors	6.940s	1486.867us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	clkmgr_csr_hw_reset	1.250s	101.396us	5	5	100.00
	clkmgr_csr_rw	1.410s	115.074us	20	20	100.00
	clkmgr_csr_aliasing	2.440s	122.726us	5	5	100.00
	clkmgr_same_csr_outstanding	3.120s	742.779us	20	20	100.00
tl_d_partial_access				50	50	100.00
	clkmgr_csr_hw_reset	1.250s	101.396us	5	5	100.00
	clkmgr_csr_rw	1.410s	115.074us	20	20	100.00
	clkmgr_csr_aliasing	2.440s	122.726us	5	5	100.00
	clkmgr_same_csr_outstanding	3.120s	742.779us	20	20	100.00

V2S

573/585 passed

97.95 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				22	25	88.00
	clkmgr_tl_intg_err	4.310s	391.478us	20	20	100.00
	clkmgr_sec_cm	3.450s	637.964us	2	5	40.00
shadow_reg_update_error				20	20	100.00
	clkmgr_shadow_reg_errors	3.720s	451.795us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	clkmgr_shadow_reg_errors	3.720s	451.795us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	clkmgr_shadow_reg_errors	3.720s	451.795us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	clkmgr_shadow_reg_errors	3.720s	451.795us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	clkmgr_shadow_reg_errors_with_csr_rw	6.640s	1859.041us	20	20	100.00
sec_cm_bus_integrity				20	20	100.00
	clkmgr_tl_intg_err	4.310s	391.478us	20	20	100.00
sec_cm_meas_clk_bkgn_chk				50	50	100.00
	clkmgr_frequency	23.190s	2472.810us	50	50	100.00
sec_cm_timeout_clk_bkgn_chk				50	50	100.00
	clkmgr_frequency_timeout	17.150s	2174.206us	50	50	100.00
sec_cm_meas_config_shadow				20	20	100.00
	clkmgr_shadow_reg_errors	3.720s	451.795us	20	20	100.00
sec_cm_idle_intersig_mubi				50	50	100.00
	clkmgr_idle_intersig_mubi	1.850s	148.083us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				50	50	100.00
	clkmgr_lc_ctrl_intersig_mubi	1.570s	127.593us	50	50	100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi				50	50	100.00
	clkmgr_lc_clk_byp_req_intersig_mubi	1.910s	235.218us	50	50	100.00
sec_cm_clk_handshake_intersig_mubi				47	50	94.00
	clkmgr_clk_handshake_intersig_mubi	1.910s	206.650us	47	50	94.00
sec_cm_div_intersig_mubi				50	50	100.00
	clkmgr_div_intersig_mubi	1.570s	173.794us	50	50	100.00
sec_cm_jitter_config_mubi				20	20	100.00
	clkmgr_csr_rw	1.410s	115.074us	20	20	100.00
sec_cm_idle_ctr_redun				2	5	40.00
	clkmgr_sec_cm	3.450s	637.964us	2	5	40.00
sec_cm_meas_config_regwen				20	20	100.00
	clkmgr_csr_rw	1.410s	115.074us	20	20	100.00
sec_cm_clk_ctrl_config_regwen				20	20	100.00
	clkmgr_csr_rw	1.410s	115.074us	20	20	100.00
prim_count_check				2	5	40.00
	clkmgr_sec_cm	3.450s	637.964us	2	5	40.00

100/100 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
regwen				50	50	100.00
	clkmgr_regwen	7.610s	1569.846us	50	50	100.00
stress_all_with_rand_reset				50	50	100.00
	clkmgr_stress_all_with_rand_reset	181.110s	62014.696us	50	50	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
	clkmgr_sec_cm	15558534988449597300499080811130939433487218807186684880231481965199388546267	94	UVM_ERROR @ 46485894 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 46485894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	15382073495433782567364755747923631803238905424925005817583991645014729755330	173	UVM_ERROR @ 276693574 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 276693574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	70020229859264759437323370628563214251480434214459920071691568062941775611987	93	UVM_ERROR @ 32535366 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 32535366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [] vs [*]) extclk_status mismatch
	clkmgr_clk_handshake_intersig_mubi	103345429234880130368839424150682669190728755863352618235124896755517608024767	71	UVM_ERROR @ 7680463 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (4 [0x4] vs 9 [0x9]) extclk_status mismatch UVM_INFO @ 7680463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_clk_handshake_intersig_mubi	71261997366777236220514325643741953190424705117121046704388371772260046640869	71	UVM_ERROR @ 21431512 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (4 [0x4] vs 9 [0x9]) extclk_status mismatch UVM_INFO @ 21431512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_clk_handshake_intersig_mubi	22613131710424720127729749581506257738243509573122251291455325494407805902007	71	UVM_ERROR @ 5711977 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (5 [0x5] vs 9 [0x9]) extclk_status mismatch UVM_INFO @ 5711977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---