Simulation Results: csrng

 
18/01/2026 00:06:04 sha: 8ead910 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.46 %
  • code
  • 96.32 %
  • assert
  • 95.85 %
  • func
  • 91.21 %
  • block
  • 98.72 %
  • line
  • 99.61 %
  • branch
  • 96.79 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.87%
V2S
99.96%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
csrng_smoke 7.000s 337.818us 50 50 100.00
csr_hw_reset 5 5 100.00
csrng_csr_hw_reset 3.000s 83.372us 5 5 100.00
csr_rw 20 20 100.00
csrng_csr_rw 3.000s 133.816us 20 20 100.00
csr_bit_bash 5 5 100.00
csrng_csr_bit_bash 37.000s 2168.100us 5 5 100.00
csr_aliasing 5 5 100.00
csrng_csr_aliasing 6.000s 392.538us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
csrng_csr_mem_rw_with_rand_reset 5.000s 233.220us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
csrng_csr_rw 3.000s 133.816us 20 20 100.00
csrng_csr_aliasing 6.000s 392.538us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 27.000s 1510.781us 200 200 100.00
alerts 500 500 100.00
csrng_alert 61.000s 4966.893us 500 500 100.00
err 500 500 100.00
csrng_err 4.000s 128.256us 500 500 100.00
cmds 50 50 100.00
csrng_cmds 238.000s 19082.011us 50 50 100.00
life cycle 50 50 100.00
csrng_cmds 238.000s 19082.011us 50 50 100.00
stress_all 48 50 96.00
csrng_stress_all 1992.000s 181874.126us 48 50 96.00
intr_test 50 50 100.00
csrng_intr_test 3.000s 13.617us 50 50 100.00
alert_test 50 50 100.00
csrng_alert_test 4.000s 65.215us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
csrng_tl_errors 11.000s 354.958us 20 20 100.00
tl_d_illegal_access 20 20 100.00
csrng_tl_errors 11.000s 354.958us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
csrng_csr_hw_reset 3.000s 83.372us 5 5 100.00
csrng_csr_rw 3.000s 133.816us 20 20 100.00
csrng_csr_aliasing 6.000s 392.538us 5 5 100.00
csrng_same_csr_outstanding 5.000s 222.738us 20 20 100.00
tl_d_partial_access 50 50 100.00
csrng_csr_hw_reset 3.000s 83.372us 5 5 100.00
csrng_csr_rw 3.000s 133.816us 20 20 100.00
csrng_csr_aliasing 6.000s 392.538us 5 5 100.00
csrng_same_csr_outstanding 5.000s 222.738us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
csrng_sec_cm 5.000s 184.597us 5 5 100.00
csrng_tl_intg_err 12.000s 1200.598us 20 20 100.00
sec_cm_config_regwen 70 70 100.00
csrng_regwen 4.000s 128.532us 50 50 100.00
csrng_csr_rw 3.000s 133.816us 20 20 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 61.000s 4966.893us 500 500 100.00
sec_cm_intersig_mubi 48 50 96.00
csrng_stress_all 1992.000s 181874.126us 48 50 96.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 27.000s 1510.781us 200 200 100.00
csrng_err 4.000s 128.256us 500 500 100.00
csrng_sec_cm 5.000s 184.597us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 27.000s 1510.781us 200 200 100.00
csrng_err 4.000s 128.256us 500 500 100.00
csrng_sec_cm 5.000s 184.597us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 27.000s 1510.781us 200 200 100.00
csrng_err 4.000s 128.256us 500 500 100.00
csrng_sec_cm 5.000s 184.597us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 27.000s 1510.781us 200 200 100.00
csrng_err 4.000s 128.256us 500 500 100.00
csrng_sec_cm 5.000s 184.597us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 27.000s 1510.781us 200 200 100.00
csrng_err 4.000s 128.256us 500 500 100.00
csrng_sec_cm 5.000s 184.597us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 61.000s 4966.893us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 27.000s 1510.781us 200 200 100.00
csrng_err 4.000s 128.256us 500 500 100.00
sec_cm_constants_lc_gated 48 50 96.00
csrng_stress_all 1992.000s 181874.126us 48 50 96.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 61.000s 4966.893us 500 500 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
csrng_tl_intg_err 12.000s 1200.598us 20 20 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 27.000s 1510.781us 200 200 100.00
csrng_err 4.000s 128.256us 500 500 100.00
csrng_sec_cm 5.000s 184.597us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 27.000s 1510.781us 200 200 100.00
csrng_err 4.000s 128.256us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 27.000s 1510.781us 200 200 100.00
csrng_err 4.000s 128.256us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 27.000s 1510.781us 200 200 100.00
csrng_err 4.000s 128.256us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 27.000s 1510.781us 200 200 100.00
csrng_err 4.000s 128.256us 500 500 100.00
csrng_sec_cm 5.000s 184.597us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 27.000s 1510.781us 200 200 100.00
csrng_err 4.000s 128.256us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
csrng_stress_all_with_rand_reset 419.000s 29154.079us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq
csrng_stress_all 90941656070387065043513177213877910429260599220714473279637937135286965764734 145
UVM_ERROR @ 11336694 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 11336694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 5374139416091409514319378223312455935542956373444212626751050762967542185192 173
UVM_ERROR @ 4234862134 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 4234862134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---