Simulation Results: edn

 
18/01/2026 00:06:04 sha: 8ead910 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.33 %
  • code
  • 95.52 %
  • assert
  • 97.61 %
  • func
  • 92.86 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.20 %
  • toggle
  • 97.12 %
  • FSM
  • 90.86 %
Validation stages
V1
100.00%
V2
99.82%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.520s 24.107us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.340s 16.666us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.320s 16.832us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.650s 2440.827us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.540s 25.083us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 2.190s 56.649us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.320s 16.832us 20 20 100.00
edn_csr_aliasing 1.540s 25.083us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 299 300 99.67
edn_genbits 277.290s 34094.011us 299 300 99.67
csrng_commands 299 300 99.67
edn_genbits 277.290s 34094.011us 299 300 99.67
genbits 299 300 99.67
edn_genbits 277.290s 34094.011us 299 300 99.67
interrupts 50 50 100.00
edn_intr 1.660s 21.349us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.780s 35.023us 200 200 100.00
errs 100 100 100.00
edn_err 1.840s 35.169us 100 100 100.00
disable 100 100 100.00
edn_disable 1.340s 13.023us 50 50 100.00
edn_disable_auto_req_mode 1.670s 200.617us 50 50 100.00
stress_all 50 50 100.00
edn_stress_all 7.290s 620.013us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.340s 15.546us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 2.730s 100.881us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.410s 1258.202us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.410s 1258.202us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.340s 16.666us 5 5 100.00
edn_csr_rw 1.320s 16.832us 20 20 100.00
edn_csr_aliasing 1.540s 25.083us 5 5 100.00
edn_same_csr_outstanding 1.710s 209.614us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.340s 16.666us 5 5 100.00
edn_csr_rw 1.320s 16.832us 20 20 100.00
edn_csr_aliasing 1.540s 25.083us 5 5 100.00
edn_same_csr_outstanding 1.710s 209.614us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_tl_intg_err 3.470s 115.565us 20 20 100.00
edn_sec_cm 12.710s 2433.401us 5 5 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.390s 21.508us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.780s 35.023us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 12.710s 2433.401us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 12.710s 2433.401us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 12.710s 2433.401us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 12.710s 2433.401us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.780s 35.023us 200 200 100.00
edn_sec_cm 12.710s 2433.401us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.780s 35.023us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 3.470s 115.565us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
edn_stress_all_with_rand_reset 108.080s 98914.431us 50 50 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout edn_reg_block.main_sm_state (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5)
edn_genbits 40929979209374483036622111540330855384906827384605132116131147725613614350622 80
UVM_FATAL @ 34094011042 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout edn_reg_block.main_sm_state (addr=0xd0c7f3c4, Comparison=CompareOpEq, exp_data=0xc1, call_count=5)
UVM_INFO @ 34094011042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---