Simulation Results: flash_ctrl

 
18/01/2026 00:06:04 sha: 8ead910 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.97 %
  • code
  • 95.90 %
  • assert
  • 96.62 %
  • func
  • 98.39 %
  • line
  • 96.08 %
  • branch
  • 97.41 %
  • cond
  • 94.82 %
  • toggle
  • 98.66 %
  • FSM
  • 92.52 %
Validation stages
V1
100.00%
V2
99.47%
V2S
99.39%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
flash_ctrl_smoke 138.720s 259.197us 50 50 100.00
smoke_hw 5 5 100.00
flash_ctrl_smoke_hw 25.390s 21.291us 5 5 100.00
csr_hw_reset 5 5 100.00
flash_ctrl_csr_hw_reset 34.080s 40.017us 5 5 100.00
csr_rw 20 20 100.00
flash_ctrl_csr_rw 14.110s 71.801us 20 20 100.00
csr_bit_bash 5 5 100.00
flash_ctrl_csr_bit_bash 69.980s 19887.288us 5 5 100.00
csr_aliasing 5 5 100.00
flash_ctrl_csr_aliasing 63.400s 3972.583us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 16.810s 252.458us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
flash_ctrl_csr_rw 14.110s 71.801us 20 20 100.00
flash_ctrl_csr_aliasing 63.400s 3972.583us 5 5 100.00
mem_walk 5 5 100.00
flash_ctrl_mem_walk 13.450s 51.905us 5 5 100.00
mem_partial_access 5 5 100.00
flash_ctrl_mem_partial_access 13.300s 53.165us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 5 5 100.00
flash_ctrl_sw_op 21.750s 76.310us 5 5 100.00
host_read_direct 5 5 100.00
flash_ctrl_host_dir_rd 73.060s 65.098us 5 5 100.00
rma_hw_if 43 43 100.00
flash_ctrl_hw_rma 2235.240s 743603.963us 3 3 100.00
flash_ctrl_hw_rma_reset 870.720s 630492.938us 20 20 100.00
flash_ctrl_lcmgr_intg 13.300s 22.665us 20 20 100.00
host_controller_arb 5 5 100.00
flash_ctrl_host_ctrl_arb 2428.660s 1756508.716us 5 5 100.00
erase_suspend 5 5 100.00
flash_ctrl_erase_suspend 386.880s 6838.305us 5 5 100.00
program_reset 30 30 100.00
flash_ctrl_prog_reset 171.070s 5350.962us 30 30 100.00
full_memory_access 5 5 100.00
flash_ctrl_full_mem_access 3072.820s 407929.610us 5 5 100.00
rd_buff_eviction 5 5 100.00
flash_ctrl_rd_buff_evict 96.720s 194.251us 5 5 100.00
rd_buff_eviction_w_ecc 99 100 99.00
flash_ctrl_rw_evict 31.960s 46.952us 39 40 97.50
flash_ctrl_rw_evict_all_en 32.320s 27.210us 40 40 100.00
flash_ctrl_re_evict 34.500s 121.036us 20 20 100.00
host_arb 20 20 100.00
flash_ctrl_phy_arb 234.560s 27394.789us 20 20 100.00
host_interleave 20 20 100.00
flash_ctrl_phy_arb 234.560s 27394.789us 20 20 100.00
memory_protection 20 20 100.00
flash_ctrl_mp_regions 483.990s 17649.196us 20 20 100.00
fetch_code 10 10 100.00
flash_ctrl_fetch_code 27.770s 536.609us 10 10 100.00
all_partitions 20 20 100.00
flash_ctrl_rand_ops 685.340s 2458.742us 20 20 100.00
error_mp 10 10 100.00
flash_ctrl_error_mp 471.600s 31885.115us 10 10 100.00
error_prog_win 10 10 100.00
flash_ctrl_error_prog_win 539.310s 819.226us 10 10 100.00
error_prog_type 5 5 100.00
flash_ctrl_error_prog_type 1461.170s 977.906us 5 5 100.00
error_read_seed 20 20 100.00
flash_ctrl_hw_read_seed_err 13.670s 187.526us 20 20 100.00
read_write_overflow 5 5 100.00
flash_ctrl_oversize_error 200.760s 2099.455us 5 5 100.00
flash_ctrl_disable 50 50 100.00
flash_ctrl_disable 23.490s 30.155us 50 50 100.00
flash_ctrl_connect 80 80 100.00
flash_ctrl_connect 16.940s 48.803us 80 80 100.00
stress_all 5 5 100.00
flash_ctrl_stress_all 703.170s 315.973us 5 5 100.00
secret_partition 130 130 100.00
flash_ctrl_hw_sec_otp 232.360s 13454.708us 50 50 100.00
flash_ctrl_otp_reset 122.580s 78.505us 80 80 100.00
isolation_partition 3 3 100.00
flash_ctrl_hw_rma 2235.240s 743603.963us 3 3 100.00
interrupts 100 100 100.00
flash_ctrl_intr_rd 190.380s 6751.806us 40 40 100.00
flash_ctrl_intr_wr 87.930s 2730.032us 10 10 100.00
flash_ctrl_intr_rd_slow_flash 335.610s 85715.930us 40 40 100.00
flash_ctrl_intr_wr_slow_flash 376.390s 92602.274us 10 10 100.00
invalid_op 20 20 100.00
flash_ctrl_invalid_op 74.010s 1423.940us 20 20 100.00
mid_op_rst 5 5 100.00
flash_ctrl_mid_op_rst 66.840s 16391.781us 5 5 100.00
double_bit_err 34 35 97.14
flash_ctrl_read_word_sweep_derr 23.060s 115.914us 5 5 100.00
flash_ctrl_ro_derr 136.660s 750.262us 10 10 100.00
flash_ctrl_rw_derr 183.130s 6081.710us 9 10 90.00
flash_ctrl_derr_detect 144.460s 718.629us 5 5 100.00
flash_ctrl_integrity 624.390s 4750.086us 5 5 100.00
single_bit_err 24 25 96.00
flash_ctrl_read_word_sweep_serr 20.060s 88.918us 5 5 100.00
flash_ctrl_ro_serr 132.920s 7801.688us 10 10 100.00
flash_ctrl_rw_serr 254.890s 3200.619us 9 10 90.00
singlebit_err_counter 5 5 100.00
flash_ctrl_serr_counter 84.420s 4723.489us 5 5 100.00
singlebit_err_address 5 5 100.00
flash_ctrl_serr_address 100.860s 1027.344us 5 5 100.00
scramble 59 62 95.16
flash_ctrl_wo 194.820s 5624.889us 20 20 100.00
flash_ctrl_write_word_sweep 10.690s 69.911us 1 1 100.00
flash_ctrl_read_word_sweep 6.530s 68.840us 1 1 100.00
flash_ctrl_ro 130.370s 4067.305us 20 20 100.00
flash_ctrl_rw 479.610s 47470.909us 17 20 85.00
filesystem_support 5 5 100.00
flash_ctrl_fs_sup 41.040s 4033.985us 5 5 100.00
rma_write_process_error 23 23 100.00
flash_ctrl_rma_err 1134.790s 81816.815us 3 3 100.00
flash_ctrl_hw_prog_rma_wipe_err 285.760s 10018.696us 20 20 100.00
alert_test 50 50 100.00
flash_ctrl_alert_test 15.140s 38.959us 50 50 100.00
intr_test 50 50 100.00
flash_ctrl_intr_test 13.760s 32.254us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
flash_ctrl_tl_errors 20.590s 217.055us 20 20 100.00
tl_d_illegal_access 20 20 100.00
flash_ctrl_tl_errors 20.590s 217.055us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
flash_ctrl_csr_hw_reset 34.080s 40.017us 5 5 100.00
flash_ctrl_csr_rw 14.110s 71.801us 20 20 100.00
flash_ctrl_csr_aliasing 63.400s 3972.583us 5 5 100.00
flash_ctrl_same_csr_outstanding 27.670s 161.493us 20 20 100.00
tl_d_partial_access 50 50 100.00
flash_ctrl_csr_hw_reset 34.080s 40.017us 5 5 100.00
flash_ctrl_csr_rw 14.110s 71.801us 20 20 100.00
flash_ctrl_csr_aliasing 63.400s 3972.583us 5 5 100.00
flash_ctrl_same_csr_outstanding 27.670s 161.493us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
flash_ctrl_shadow_reg_errors 110.400s 53.729us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
flash_ctrl_shadow_reg_errors 110.400s 53.729us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
flash_ctrl_shadow_reg_errors 110.400s 53.729us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
flash_ctrl_shadow_reg_errors 110.400s 53.729us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 74.600s 358.539us 20 20 100.00
tl_intg_err 25 25 100.00
flash_ctrl_tl_intg_err 560.100s 1020.226us 20 20 100.00
flash_ctrl_sec_cm 2616.060s 1639.042us 5 5 100.00
sec_cm_reg_bus_integrity 20 20 100.00
flash_ctrl_tl_intg_err 560.100s 1020.226us 20 20 100.00
sec_cm_host_bus_integrity 20 20 100.00
flash_ctrl_tl_intg_err 560.100s 1020.226us 20 20 100.00
sec_cm_mem_bus_integrity 6 6 100.00
flash_ctrl_rd_intg 31.950s 69.464us 3 3 100.00
flash_ctrl_wr_intg 11.350s 91.261us 3 3 100.00
sec_cm_scramble_key_sideload 50 50 100.00
flash_ctrl_smoke 138.720s 259.197us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 260 260 100.00
flash_ctrl_otp_reset 122.580s 78.505us 80 80 100.00
flash_ctrl_disable 23.490s 30.155us 50 50 100.00
flash_ctrl_sec_info_access 83.500s 15775.287us 50 50 100.00
flash_ctrl_connect 16.940s 48.803us 80 80 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
flash_ctrl_config_regwen 11.860s 78.722us 5 5 100.00
sec_cm_data_regions_config_regwen 20 20 100.00
flash_ctrl_csr_rw 14.110s 71.801us 20 20 100.00
sec_cm_data_regions_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 110.400s 53.729us 20 20 100.00
sec_cm_info_regions_config_regwen 20 20 100.00
flash_ctrl_csr_rw 14.110s 71.801us 20 20 100.00
sec_cm_info_regions_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 110.400s 53.729us 20 20 100.00
sec_cm_bank_config_regwen 20 20 100.00
flash_ctrl_csr_rw 14.110s 71.801us 20 20 100.00
sec_cm_bank_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 110.400s 53.729us 20 20 100.00
sec_cm_mem_ctrl_global_esc 50 50 100.00
flash_ctrl_disable 23.490s 30.155us 50 50 100.00
sec_cm_mem_ctrl_local_esc 6 6 100.00
flash_ctrl_rd_intg 31.950s 69.464us 3 3 100.00
flash_ctrl_access_after_disable 11.030s 23.725us 3 3 100.00
sec_cm_mem_addr_infection 3 3 100.00
flash_ctrl_host_addr_infection 17.280s 58.345us 3 3 100.00
sec_cm_mem_disable_config_mubi 50 50 100.00
flash_ctrl_disable 23.490s 30.155us 50 50 100.00
sec_cm_exec_config_redun 10 10 100.00
flash_ctrl_fetch_code 27.770s 536.609us 10 10 100.00
sec_cm_mem_scramble 17 20 85.00
flash_ctrl_rw 479.610s 47470.909us 17 20 85.00
sec_cm_mem_integrity 23 25 92.00
flash_ctrl_rw_serr 254.890s 3200.619us 9 10 90.00
flash_ctrl_rw_derr 183.130s 6081.710us 9 10 90.00
flash_ctrl_integrity 624.390s 4750.086us 5 5 100.00
sec_cm_rma_entry_mem_sec_wipe 3 3 100.00
flash_ctrl_hw_rma 2235.240s 743603.963us 3 3 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2616.060s 1639.042us 5 5 100.00
sec_cm_phy_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2616.060s 1639.042us 5 5 100.00
sec_cm_phy_prog_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2616.060s 1639.042us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
flash_ctrl_sec_cm 2616.060s 1639.042us 5 5 100.00
sec_cm_phy_arbiter_ctrl_redun 5 5 100.00
flash_ctrl_phy_arb_redun 17.710s 873.420us 5 5 100.00
sec_cm_phy_host_grant_ctrl_consistency 5 5 100.00
flash_ctrl_phy_host_grant_err 12.620s 59.677us 5 5 100.00
sec_cm_phy_ack_ctrl_consistency 5 5 100.00
flash_ctrl_phy_ack_consistency 13.150s 22.449us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
flash_ctrl_sec_cm 2616.060s 1639.042us 5 5 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2616.060s 1639.042us 5 5 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2616.060s 1639.042us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 23.370s 89.401us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 3 3 100.00
flash_ctrl_basic_rw 470.720s 878.633us 3 3 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes
flash_ctrl_rw 42733807682115212771027463509552362156374364994343837040104186248656050418097 None
Job timed out after 60 minutes
flash_ctrl_rw_derr 111204765519045198160198755300715702848498355683596575826174006473806732966449 None
Job timed out after 60 minutes
flash_ctrl_rw 48430043043235224179193858758415048563332232943066206483182028631731056110717 None
Job timed out after 60 minutes
flash_ctrl_rw_serr 71282399601723584741961001251178087807596195328494666385250569995632602131140 None
Job timed out after 60 minutes
flash_ctrl_rw 100923482673849468735714293784342344308109301071592098897048295501991777226233 None
Job timed out after 60 minutes
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: *
flash_ctrl_rw_evict 82286457097067284849427444030973534914859134794757684223471114370471478173528 105
UVM_ERROR @ 52182.7 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 52182.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---