Simulation Results: hmac

 
18/01/2026 00:06:04 sha: 8ead910 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.97 %
  • code
  • 99.30 %
  • assert
  • 97.61 %
  • func
  • 100.00 %
  • line
  • 99.95 %
  • branch
  • 99.83 %
  • cond
  • 96.74 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 15.690s 3417.314us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.000s 43.204us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 0.830s 113.858us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 10.210s 13223.935us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 5.300s 566.582us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 447.840s 109266.752us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 0.830s 113.858us 20 20 100.00
hmac_csr_aliasing 5.300s 566.582us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 104.140s 3430.810us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 102.260s 18653.938us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 245.180s 32598.919us 30 30 100.00
hmac_test_sha384_vectors 530.610s 14842.945us 75 75 100.00
hmac_test_sha512_vectors 542.320s 29133.696us 75 75 100.00
hmac_test_hmac256_vectors 14.690s 746.812us 50 50 100.00
hmac_test_hmac384_vectors 15.870s 1326.604us 60 60 100.00
hmac_test_hmac512_vectors 17.020s 350.392us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 47.410s 2038.350us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1251.350s 15492.271us 10 10 100.00
error 10 10 100.00
hmac_error 61.760s 5122.769us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 93.390s 6672.978us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 15.690s 3417.314us 10 10 100.00
hmac_long_msg 104.140s 3430.810us 10 10 100.00
hmac_back_pressure 102.260s 18653.938us 25 25 100.00
hmac_datapath_stress 1251.350s 15492.271us 10 10 100.00
hmac_burst_wr 47.410s 2038.350us 50 50 100.00
hmac_stress_all 3780.010s 27575.152us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 15.690s 3417.314us 10 10 100.00
hmac_long_msg 104.140s 3430.810us 10 10 100.00
hmac_back_pressure 102.260s 18653.938us 25 25 100.00
hmac_datapath_stress 1251.350s 15492.271us 10 10 100.00
hmac_wipe_secret 93.390s 6672.978us 10 10 100.00
hmac_test_sha256_vectors 245.180s 32598.919us 30 30 100.00
hmac_test_sha384_vectors 530.610s 14842.945us 75 75 100.00
hmac_test_sha512_vectors 542.320s 29133.696us 75 75 100.00
hmac_test_hmac256_vectors 14.690s 746.812us 50 50 100.00
hmac_test_hmac384_vectors 15.870s 1326.604us 60 60 100.00
hmac_test_hmac512_vectors 17.020s 350.392us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 15.690s 3417.314us 10 10 100.00
hmac_long_msg 104.140s 3430.810us 10 10 100.00
hmac_back_pressure 102.260s 18653.938us 25 25 100.00
hmac_datapath_stress 1251.350s 15492.271us 10 10 100.00
hmac_burst_wr 47.410s 2038.350us 50 50 100.00
hmac_error 61.760s 5122.769us 10 10 100.00
hmac_wipe_secret 93.390s 6672.978us 10 10 100.00
hmac_test_sha256_vectors 245.180s 32598.919us 30 30 100.00
hmac_test_sha384_vectors 530.610s 14842.945us 75 75 100.00
hmac_test_sha512_vectors 542.320s 29133.696us 75 75 100.00
hmac_test_hmac256_vectors 14.690s 746.812us 50 50 100.00
hmac_test_hmac384_vectors 15.870s 1326.604us 60 60 100.00
hmac_test_hmac512_vectors 17.020s 350.392us 75 75 100.00
hmac_stress_all 3780.010s 27575.152us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 3780.010s 27575.152us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.930s 12.948us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.700s 31.135us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 3.290s 240.875us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 3.290s 240.875us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.000s 43.204us 5 5 100.00
hmac_csr_rw 0.830s 113.858us 20 20 100.00
hmac_csr_aliasing 5.300s 566.582us 5 5 100.00
hmac_same_csr_outstanding 1.790s 119.094us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.000s 43.204us 5 5 100.00
hmac_csr_rw 0.830s 113.858us 20 20 100.00
hmac_csr_aliasing 5.300s 566.582us 5 5 100.00
hmac_same_csr_outstanding 1.790s 119.094us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_tl_intg_err 3.000s 304.105us 20 20 100.00
hmac_sec_cm 1.410s 522.380us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 3.000s 304.105us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 15.690s 3417.314us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 6.830s 123.899us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 378.350s 5617.366us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.780s 10.876us 1 1 100.00

Error Messages

   Test seed line log context