Simulation Results: keymgr

 
18/01/2026 00:06:04 sha: 8ead910 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.96 %
  • code
  • 98.99 %
  • assert
  • 97.72 %
  • func
  • 91.18 %
  • line
  • 99.13 %
  • branch
  • 99.01 %
  • cond
  • 98.18 %
  • toggle
  • 98.62 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.29%
V2S
99.81%
V3
52.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_smoke 9.690s 3227.568us 50 50 100.00
random 50 50 100.00
keymgr_random 32.930s 2033.071us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 1.030s 32.750us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 1.450s 51.844us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 10.920s 1329.720us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 7.130s 458.720us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 1.830s 41.526us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 1.450s 51.844us 20 20 100.00
keymgr_csr_aliasing 7.130s 458.720us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 80.310s 39528.480us 50 50 100.00
sideload 200 200 100.00
keymgr_sideload 21.310s 5577.754us 50 50 100.00
keymgr_sideload_kmac 25.900s 15132.374us 50 50 100.00
keymgr_sideload_aes 38.720s 5222.706us 50 50 100.00
keymgr_sideload_otbn 53.210s 6989.793us 50 50 100.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 15.110s 1543.512us 50 50 100.00
lc_disable 49 50 98.00
keymgr_lc_disable 22.320s 697.815us 49 50 98.00
kmac_error_response 49 50 98.00
keymgr_kmac_rsp_err 8.170s 249.906us 49 50 98.00
invalid_sw_input 50 50 100.00
keymgr_sw_invalid_input 38.450s 7830.886us 50 50 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 28.720s 2729.757us 50 50 100.00
sync_async_fault_cross 49 50 98.00
keymgr_sync_async_fault_cross 15.230s 2090.014us 49 50 98.00
stress_all 47 50 94.00
keymgr_stress_all 95.600s 26659.891us 47 50 94.00
intr_test 50 50 100.00
keymgr_intr_test 0.990s 30.223us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.400s 24.906us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 3.520s 274.727us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 3.520s 274.727us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 1.030s 32.750us 5 5 100.00
keymgr_csr_rw 1.450s 51.844us 20 20 100.00
keymgr_csr_aliasing 7.130s 458.720us 5 5 100.00
keymgr_same_csr_outstanding 3.520s 1474.017us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 1.030s 32.750us 5 5 100.00
keymgr_csr_rw 1.450s 51.844us 20 20 100.00
keymgr_csr_aliasing 7.130s 458.720us 5 5 100.00
keymgr_same_csr_outstanding 3.520s 1474.017us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 23.310s 3317.843us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_sec_cm 23.310s 3317.843us 5 5 100.00
keymgr_tl_intg_err 4.890s 1551.620us 20 20 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 4.530s 478.037us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 4.530s 478.037us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 4.530s 478.037us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 4.530s 478.037us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 13.720s 1060.602us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 23.310s 3317.843us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 23.310s 3317.843us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 4.890s 1551.620us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 4.530s 478.037us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 80.310s 39528.480us 50 50 100.00
sec_cm_reseed_config_regwen 70 70 100.00
keymgr_random 32.930s 2033.071us 50 50 100.00
keymgr_csr_rw 1.450s 51.844us 20 20 100.00
sec_cm_sw_binding_config_regwen 70 70 100.00
keymgr_random 32.930s 2033.071us 50 50 100.00
keymgr_csr_rw 1.450s 51.844us 20 20 100.00
sec_cm_max_key_ver_config_regwen 70 70 100.00
keymgr_random 32.930s 2033.071us 50 50 100.00
keymgr_csr_rw 1.450s 51.844us 20 20 100.00
sec_cm_lc_ctrl_intersig_mubi 49 50 98.00
keymgr_lc_disable 22.320s 697.815us 49 50 98.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 28.720s 2729.757us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 28.720s 2729.757us 50 50 100.00
sec_cm_hw_key_sw_noaccess 50 50 100.00
keymgr_random 32.930s 2033.071us 50 50 100.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 20.410s 2217.633us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 23.310s 3317.843us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 23.310s 3317.843us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 23.310s 3317.843us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 13.090s 2769.943us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 49 50 98.00
keymgr_lc_disable 22.320s 697.815us 49 50 98.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 23.310s 3317.843us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 23.310s 3317.843us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 23.310s 3317.843us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 13.090s 2769.943us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 13.090s 2769.943us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 23.310s 3317.843us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 13.090s 2769.943us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 23.310s 3317.843us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 13.090s 2769.943us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 26 50 52.00
keymgr_stress_all_with_rand_reset 19.510s 1708.025us 26 50 52.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 74170360370317520272061927023980833811881378641747155928209900647968014176535 588
UVM_ERROR @ 214964005 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 214964005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 28805618721286141109326193140028142234782121593707946826576438521099220269200 271
UVM_ERROR @ 118525100 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 118525100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 97062951408743565243322001300545994714159572330732572977849644360164386278310 687
UVM_ERROR @ 292566517 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 292566517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 67127505393116067561027206265283082743601836453720127003604056716371302526056 326
UVM_ERROR @ 144441724 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 144441724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 71135572369060366127338305764704154951047224872155762355083442083678251785054 94
UVM_ERROR @ 108478684 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 108478684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 18217917967422875801412794314637356219985018340795272841126445749156802836129 190
UVM_ERROR @ 462409959 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 462409959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 2732686629807905862754705755039917849214013003862068937453958133406546266082 471
UVM_ERROR @ 292905167 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 292905167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 101211157747127935106812803975722512350531502533648142347784002445594936262975 114
UVM_ERROR @ 1221148348 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1221148348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 63079130183804856718674369768748801785964718539564772051297931489361537405031 825
UVM_ERROR @ 1271687196 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1271687196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 43484744958866538481774760057997991767746617879350930520918851579847819347761 399
UVM_ERROR @ 171459819 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 171459819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 75892985084910022921800049631036464415923205129312028142352235715294792563284 496
UVM_ERROR @ 743262765 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 743262765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 53319508013280509542755687542988312149688365438801110727632356547624576381735 355
UVM_ERROR @ 229520403 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 229520403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 62365536713772806117804105050139704826160882574420536057448868471688992728544 495
UVM_ERROR @ 514343851 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 514343851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 75656265523591042780804625094542881902237331450101511609632856219878461189062 527
UVM_ERROR @ 219238920 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 219238920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 82771019981881144525913337156249004341757953230293409143971394515985838764478 314
UVM_ERROR @ 200869625 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 200869625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 48980853809915923182906772903956903072009602003729776251149019163402558359491 191
UVM_ERROR @ 108787360 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 108787360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 76466243579327883919433040848957486522143067840593780367558484682946038858669 472
UVM_ERROR @ 324803740 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 324803740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 38109018741708115190717266579091130659645593184740179752778958163487656648174 160
UVM_ERROR @ 158624309 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 158624309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 26114670748881902503742463381731454667170251613910522608303033187691366776117 363
UVM_ERROR @ 821881656 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 821881656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 70054821478112512491333472255581497481741348226986006396717089263777749124482 276
UVM_ERROR @ 522690015 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 522690015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 103370712774651371914400206742212362398620322451911902312422603054912098486816 809
UVM_ERROR @ 3347920214 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3347920214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 53279100623352857090466807881582887365074251855821645074586964688339366923502 94
UVM_ERROR @ 113779185 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 113779185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share0_output_*
keymgr_lc_disable 72611049370651966028924808829430572727178299022289320366145190569371686581565 155
UVM_ERROR @ 84919383 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (866595533 [0x33a732cd] vs 866595533 [0x33a732cd]) reg name: keymgr_reg_block.sw_share0_output_4
UVM_INFO @ 84919383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly
keymgr_kmac_rsp_err 42862083866876487652633231333903317834657478339062158287279214264110816639740 427
UVM_ERROR @ 275913462 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
UVM_INFO @ 275913462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_binding_regwen
keymgr_stress_all_with_rand_reset 35244732379259177324000323053358942421176790245016343909798403754197267792185 1426
UVM_ERROR @ 182701267 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.sw_binding_regwen
UVM_INFO @ 182701267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_stress_all 33914036211709588782015172446850377374832014380916966460453659466503470435579 469
UVM_ERROR @ 890897192 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 890897192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all 53595423910527091054064538081366595989296392564227416847390317241833003594098 3620
UVM_ERROR @ 549258024 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 549258024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1142) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
keymgr_stress_all_with_rand_reset 91375700922164992418488304634476004233587115163825328760638894691495445485092 1027
UVM_ERROR @ 3610855015 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3610855015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert recov_operation_err is not received!
keymgr_sync_async_fault_cross 76861182000367138600049975056643964826019462542818140775973770381211283247824 204
UVM_ERROR @ 47504788 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
UVM_INFO @ 47504788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_*
keymgr_stress_all 48754065331123440069632970901863498289085285078717616691201348269978139189747 1822
UVM_ERROR @ 733611307 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_6
UVM_INFO @ 733611307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---