Simulation Results: kmac

 
18/01/2026 00:06:04 sha: 8ead910 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.68 %
  • code
  • 94.35 %
  • assert
  • 97.83 %
  • func
  • 97.86 %
  • line
  • 99.27 %
  • branch
  • 97.15 %
  • cond
  • 94.45 %
  • toggle
  • 99.89 %
  • FSM
  • 80.99 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 81.780s 4341.244us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.490s 42.054us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.490s 29.795us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 21.860s 5999.912us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 8.620s 400.703us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 3.010s 93.144us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.490s 29.795us 20 20 100.00
kmac_csr_aliasing 8.620s 400.703us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.080s 14.340us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.930s 46.743us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 3837.530s 482451.251us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1334.010s 163101.061us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 1633.190s 18496.031us 5 5 100.00
kmac_test_vectors_sha3_256 1597.730s 19536.069us 5 5 100.00
kmac_test_vectors_sha3_384 1946.950s 490614.343us 5 5 100.00
kmac_test_vectors_sha3_512 1214.170s 44147.949us 5 5 100.00
kmac_test_vectors_shake_128 2428.660s 105333.981us 5 5 100.00
kmac_test_vectors_shake_256 1965.020s 358263.461us 5 5 100.00
kmac_test_vectors_kmac 3.500s 294.006us 5 5 100.00
kmac_test_vectors_kmac_xof 3.480s 217.273us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 510.650s 81536.442us 50 50 100.00
app 50 50 100.00
kmac_app 374.280s 19088.989us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 314.530s 16263.525us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 414.270s 28021.144us 50 50 100.00
error 50 50 100.00
kmac_error 478.690s 82591.561us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 19.520s 7541.885us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 10.400s 840.558us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 55.330s 9672.593us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 37.700s 1650.547us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 87.740s 29059.984us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 42.040s 12739.989us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2081.430s 224984.642us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.190s 72.251us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.260s 31.742us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 4.460s 624.668us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 4.460s 624.668us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.490s 42.054us 5 5 100.00
kmac_csr_rw 1.490s 29.795us 20 20 100.00
kmac_csr_aliasing 8.620s 400.703us 5 5 100.00
kmac_same_csr_outstanding 3.000s 268.092us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.490s 42.054us 5 5 100.00
kmac_csr_rw 1.490s 29.795us 20 20 100.00
kmac_csr_aliasing 8.620s 400.703us 5 5 100.00
kmac_same_csr_outstanding 3.000s 268.092us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.730s 101.739us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.730s 101.739us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.730s 101.739us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.730s 101.739us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 6.030s 483.827us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 5.470s 915.533us 20 20 100.00
kmac_sec_cm 112.750s 33522.593us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 5.470s 915.533us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 42.040s 12739.989us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 81.780s 4341.244us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 510.650s 81536.442us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.730s 101.739us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 112.750s 33522.593us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 112.750s 33522.593us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 112.750s 33522.593us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 81.780s 4341.244us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 42.040s 12739.989us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 112.750s 33522.593us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 272.840s 20632.518us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 81.780s 4341.244us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
kmac_stress_all_with_rand_reset 333.030s 5860.476us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 78026372220777546937021395785924021314885547758413626146120465032162324254856 514
UVM_ERROR @ 5860475892 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 5860475892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---