Simulation Results: kmac

 
18/01/2026 00:06:04 sha: 8ead910 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.40 %
  • code
  • 92.34 %
  • assert
  • 97.74 %
  • func
  • 96.12 %
  • line
  • 97.69 %
  • branch
  • 96.04 %
  • cond
  • 94.41 %
  • toggle
  • 100.00 %
  • FSM
  • 73.55 %
Validation stages
V1
100.00%
V2
98.10%
V2S
100.00%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 71.270s 4331.009us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 0.900s 61.554us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 0.990s 63.023us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 17.110s 15981.519us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 5.610s 385.719us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 1.930s 137.347us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 0.990s 63.023us 20 20 100.00
kmac_csr_aliasing 5.610s 385.719us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 0.770s 20.432us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.160s 184.125us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 2964.920s 330626.572us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 906.700s 127814.466us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 1495.580s 80452.447us 5 5 100.00
kmac_test_vectors_sha3_256 2112.140s 981332.416us 5 5 100.00
kmac_test_vectors_sha3_384 1278.170s 186828.072us 5 5 100.00
kmac_test_vectors_sha3_512 635.940s 9339.137us 5 5 100.00
kmac_test_vectors_shake_128 1412.130s 87435.147us 5 5 100.00
kmac_test_vectors_shake_256 1865.640s 167317.669us 5 5 100.00
kmac_test_vectors_kmac 2.510s 36.447us 5 5 100.00
kmac_test_vectors_kmac_xof 3.360s 442.602us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 414.900s 86020.523us 50 50 100.00
app 50 50 100.00
kmac_app 334.770s 55938.600us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 214.710s 59412.579us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 311.690s 31584.447us 50 50 100.00
error 50 50 100.00
kmac_error 455.600s 83109.224us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 14.150s 7705.441us 50 50 100.00
sideload_invalid 34 50 68.00
kmac_sideload_invalid 121.950s 10009.543us 34 50 68.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 41.020s 11678.090us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 33.040s 6164.717us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 51.740s 7137.750us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 45.780s 831.052us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2220.290s 296210.223us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 0.860s 14.642us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.190s 38.053us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 2.560s 62.526us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 2.560s 62.526us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 0.900s 61.554us 5 5 100.00
kmac_csr_rw 0.990s 63.023us 20 20 100.00
kmac_csr_aliasing 5.610s 385.719us 5 5 100.00
kmac_same_csr_outstanding 2.000s 123.492us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 0.900s 61.554us 5 5 100.00
kmac_csr_rw 0.990s 63.023us 20 20 100.00
kmac_csr_aliasing 5.610s 385.719us 5 5 100.00
kmac_same_csr_outstanding 2.000s 123.492us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 1.780s 431.108us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 1.780s 431.108us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 1.780s 431.108us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 1.780s 431.108us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 3.840s 776.644us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_tl_intg_err 3.580s 976.699us 20 20 100.00
kmac_sec_cm 71.020s 43928.774us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 3.580s 976.699us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 45.780s 831.052us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 71.270s 4331.009us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 414.900s 86020.523us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 1.780s 431.108us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 71.020s 43928.774us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 71.020s 43928.774us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 71.020s 43928.774us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 71.270s 4331.009us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 45.780s 831.052us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 71.020s 43928.774us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 285.150s 20266.190us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 71.270s 4331.009us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 6 10 60.00
kmac_stress_all_with_rand_reset 350.570s 24531.223us 6 10 60.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5)
kmac_sideload_invalid 74833071592728841964779158330588541397243150303917466287327730755483826571771 79
UVM_FATAL @ 10173189710 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x80400000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
UVM_INFO @ 10173189710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 24349438003636006148926357575818285254649484428078186138610304068087229408766 79
UVM_FATAL @ 10039273342 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xcd2f0000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
UVM_INFO @ 10039273342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 19675003531711798765233772024880709185673012571199836873235204308922248574896 79
UVM_FATAL @ 10036972335 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xab075000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
UVM_INFO @ 10036972335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 444388549943069709039631072439822493423252015249105859124297967009558143216 200
UVM_ERROR @ 4121383379 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4121383379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 60424219035643876421317216540709944052766239178711384370895209133769026324859 201
UVM_ERROR @ 5548663918 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5548663918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 72148324842307347314336800788601997200088167299242933221451026717075263233821 311
UVM_ERROR @ 18157673166 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 18157673166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15)
kmac_sideload_invalid 52059325517254382752916143526139812593763085713974197935591092523770899701900 90
UVM_FATAL @ 10129865488 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7c3bc000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
UVM_INFO @ 10129865488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2)
kmac_sideload_invalid 113340916241811012852073319981144524146254722618759827595699668937722038331751 75
UVM_FATAL @ 10066406983 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x67c85000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10066406983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 31551877467770844946564799064262332518360552639506968342638848416196857869687 75
UVM_FATAL @ 10017187893 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7c481000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10017187893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 110973990975229470525863456637294964624399195820961913264217350943211008824473 75
UVM_FATAL @ 10009542923 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x62823000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10009542923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 89791575429296744465613216661316272082578140171278585077830846037188346764295 75
UVM_FATAL @ 10017702964 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa72d000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10017702964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 111787557789904409542360179877368413020902220104407539353374923767801998428341 247
UVM_ERROR @ 1295514141 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 1295514141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6)
kmac_sideload_invalid 48037018126356030372658843116896865235843494627263926344491010768960984686248 80
UVM_FATAL @ 10088358014 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb172b000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10088358014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 54295439167520912064876997218169903672254020866046421298323096604683238319889 79
UVM_FATAL @ 10145691580 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x60659000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10145691580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
kmac_sideload_invalid 91695502299691738847762535649909230438536576150728701846625216725954103206275 76
UVM_FATAL @ 10029862852 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xae337000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 10029862852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)
kmac_sideload_invalid 107758189127551753806744860470110680772691319842587596173547337735861411137789 80
UVM_FATAL @ 10052669016 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6e0c7000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10052669016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21)
kmac_sideload_invalid 71553255917388597278438732336269056656204232971866809541588914408849598249328 97
UVM_FATAL @ 10525172673 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe9f0c000, Comparison=CompareOpEq, exp_data=0x1, call_count=21)
UVM_INFO @ 10525172673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11)
kmac_sideload_invalid 50362227665539735439156929769170604549931091158910705675119714395508329639816 84
UVM_FATAL @ 10150515122 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xbad5b000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
UVM_INFO @ 10150515122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18)
kmac_sideload_invalid 97446801397017263274335254199692400349713231626020539811408090438953874512208 93
UVM_FATAL @ 10137404574 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2f97b000, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
UVM_INFO @ 10137404574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14)
kmac_sideload_invalid 33846142038185116968193404411296246380871344898971660701555887737118463769573 88
UVM_FATAL @ 10134023267 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5ba06000, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
UVM_INFO @ 10134023267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---