Simulation Results: otbn

 
18/01/2026 00:06:04 sha: 8ead910 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.73 %
  • code
  • 96.35 %
  • assert
  • 96.84 %
  • func
  • 100.00 %
  • block
  • 99.56 %
  • line
  • 99.65 %
  • branch
  • 94.80 %
  • toggle
  • 93.51 %
  • FSM
  • 97.44 %
Validation stages
V1
99.48%
V2
98.84%
V2S
98.94%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 1 0.00
otbn_smoke 14.760s 0.000us 0 1 0.00
single_binary 100 100 100.00
otbn_single 30.000s 543.611us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 5.000s 22.010us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 6.000s 26.686us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 8.000s 100.091us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 4.000s 17.833us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 7.000s 243.250us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 6.000s 26.686us 20 20 100.00
otbn_csr_aliasing 4.000s 17.833us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 26.000s 3896.120us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 21.000s 544.381us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 159.000s 721.046us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 48.000s 317.532us 1 1 100.00
back_to_back 9 10 90.00
otbn_multi 171.000s 824.887us 9 10 90.00
stress_all 10 10 100.00
otbn_stress_all 96.000s 382.029us 10 10 100.00
lc_escalation 57 60 95.00
otbn_escalate 24.000s 614.329us 57 60 95.00
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 11.000s 37.262us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 90.000s 1260.913us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 6.000s 20.385us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 5.000s 41.184us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 10.000s 105.494us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 10.000s 105.494us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 5.000s 22.010us 5 5 100.00
otbn_csr_rw 6.000s 26.686us 20 20 100.00
otbn_csr_aliasing 4.000s 17.833us 5 5 100.00
otbn_same_csr_outstanding 5.000s 26.817us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 5.000s 22.010us 5 5 100.00
otbn_csr_rw 6.000s 26.686us 20 20 100.00
otbn_csr_aliasing 4.000s 17.833us 5 5 100.00
otbn_same_csr_outstanding 5.000s 26.817us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 12.000s 38.167us 10 10 100.00
otbn_dmem_err 13.000s 38.368us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 11.000s 66.378us 5 5 100.00
otbn_controller_ispr_rdata_err 14.000s 42.689us 5 5 100.00
otbn_mac_bignum_acc_err 76.000s 270.184us 5 5 100.00
otbn_urnd_err 14.000s 56.322us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 7.000s 19.531us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 6.000s 164.530us 2 2 100.00
otbn_non_sec_partial_wipe 9 10 90.00
otbn_partial_wipe 7.000s 19.683us 9 10 90.00
tl_intg_err 25 25 100.00
otbn_sec_cm 796.000s 4593.506us 5 5 100.00
otbn_tl_intg_err 33.000s 297.283us 20 20 100.00
passthru_mem_tl_intg_err 16 20 80.00
otbn_passthru_mem_tl_intg_err 48.000s 283.846us 16 20 80.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 796.000s 4593.506us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 796.000s 4593.506us 5 5 100.00
sec_cm_mem_scramble 0 1 0.00
otbn_smoke 14.760s 0.000us 0 1 0.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 13.000s 38.368us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 12.000s 38.167us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 33.000s 297.283us 20 20 100.00
sec_cm_controller_fsm_global_esc 57 60 95.00
otbn_escalate 24.000s 614.329us 57 60 95.00
sec_cm_controller_fsm_local_esc 40 40 100.00
otbn_imem_err 12.000s 38.167us 10 10 100.00
otbn_dmem_err 13.000s 38.368us 15 15 100.00
otbn_zero_state_err_urnd 11.000s 37.262us 5 5 100.00
otbn_illegal_mem_acc 7.000s 19.531us 5 5 100.00
otbn_sec_cm 796.000s 4593.506us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 796.000s 4593.506us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 30.000s 543.611us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 12.000s 38.167us 10 10 100.00
otbn_dmem_err 13.000s 38.368us 15 15 100.00
otbn_zero_state_err_urnd 11.000s 37.262us 5 5 100.00
otbn_illegal_mem_acc 7.000s 19.531us 5 5 100.00
otbn_sec_cm 796.000s 4593.506us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 796.000s 4593.506us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 57 60 95.00
otbn_escalate 24.000s 614.329us 57 60 95.00
sec_cm_start_stop_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 12.000s 38.167us 10 10 100.00
otbn_dmem_err 13.000s 38.368us 15 15 100.00
otbn_zero_state_err_urnd 11.000s 37.262us 5 5 100.00
otbn_illegal_mem_acc 7.000s 19.531us 5 5 100.00
otbn_sec_cm 796.000s 4593.506us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 796.000s 4593.506us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 30.000s 543.611us 100 100 100.00
sec_cm_ctrl_redun 11 12 91.67
otbn_ctrl_redun 9.000s 22.284us 11 12 91.67
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 7.000s 13.976us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 39.000s 238.769us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 39.000s 238.769us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 11.000s 43.289us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 796.000s 4593.506us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 796.000s 4593.506us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 13.000s 258.004us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 796.000s 4593.506us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 796.000s 4593.506us 5 5 100.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 14.000s 35.902us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 14.000s 35.902us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 14.000s 113.744us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 30.000s 543.611us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 30.000s 543.611us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 30.000s 543.611us 100 100 100.00
sec_cm_write_mem_integrity 9 10 90.00
otbn_multi 171.000s 824.887us 9 10 90.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 30.000s 543.611us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 30.000s 543.611us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 19.000s 29.669us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 30.000s 543.611us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 796.000s 4593.506us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
otbn_stress_all_with_rand_reset 388.000s 6228.875us 4 10 40.00

Error Messages

   Test seed line log context
Job returned non-zero exit code
otbn_smoke 50907820130906726706916607052982494255103418984781068492469330219531358358100 None
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --src-dir /nightly/current_run/opentitan/hw/ip/otbn/dv/smoke /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_smoke/latest/otbn-binaries' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_smoke/latest run_opts='+otbn_elf_dir=/nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_smoke/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=439798356 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_smoke.439798356 -covworkdir /nightly/current_run/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_smoke.439798356 -covoverwrite' seed=50907820130906726706916607052982494255103418984781068492469330219531358358100 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_smoke_vseq
[make]: pre_run
mkdir -p /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_smoke/latest
cd /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_smoke/latest && pushd /nightly/current_run/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/current_run/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --src-dir /nightly/current_run/opentitan/hw/ip/otbn/dv/smoke /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_smoke/latest/otbn-binaries
/nightly/current_run/opentitan /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_smoke/latest
2026/01/18 13:07:16 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.
otbn_multi 40079503400239823882435866145838267384564636411427836488419331722350715198217 148
UVM_FATAL @ 76223192 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 76223192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 71756741869744354555673216302416213723228083298582497591940003198275418845303 88
UVM_FATAL @ 13577522 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 13577522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 106938323430572711732895268911336226697007984316797988826889689423368480841656 83
UVM_FATAL @ 1067480 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 1067480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 42992954571754574622438222469884376423016674502093272748886021297264656084661 113
UVM_FATAL @ 109769007 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 109769007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 63101118587985954509917006016125708695485161610452801248439782117081148290532 103
UVM_FATAL @ 42397122 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
UVM_INFO @ 42397122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 73595663111352663257207280231159473016364592334858917592667715971688830866353 166
UVM_FATAL @ 45455372 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 45455372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 25074741843209684705153735438411568986535871245784113803949977478761337670135 279
UVM_ERROR @ 400905399 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 400905399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 76327082024652244857338506616363970151987839970917252488782762735572819490580 487
UVM_ERROR @ 6304775779 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6304775779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 72452729561479908171456309491242195648865577393925015131163835165911639583018 164
UVM_ERROR @ 833288426 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 833288426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 41117964549860172283705502846711732091606783993235537107079868815261245823364 670
UVM_ERROR @ 6228874822 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6228874822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,1015): Assertion OnlyWriteLoadDataBaseWhenDMemValid_A has failed
otbn_ctrl_redun 14964713090153536752424045310945546240982813625291266374855678001724138879371 108
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,1015): (time 340059752 PS) Assertion tb.dut.u_otbn_core.OnlyWriteLoadDataBaseWhenDMemValid_A has failed
UVM_ERROR @ 340059752 ps: (otbn_core.sv:1015) [ASSERT FAILED] OnlyWriteLoadDataBaseWhenDMemValid_A
UVM_INFO @ 340059752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
otbn_stress_all_with_rand_reset 51828628738665253623072721088236367200421803440468891326339166833441617030899 149
UVM_FATAL @ 14882923 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 14882923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status
otbn_partial_wipe 6566600290165716000640132802537465626515009622653193599446525666234498276215 111
UVM_ERROR @ 12113437 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (1 [0x1] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 12113437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 60112530755711905344034489097649617784465074074958711766908520266643991560136 110
UVM_ERROR @ 13445587 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 13445587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 12356652214997185102281313472642782363908775179124293725488352457508100063383 111
UVM_ERROR @ 1611846 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 1611846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_escalate 81139711772581421231676612149776725067202773629047065989380217063176955936038 118
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 22480701 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 22480701 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 22480701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---