rom_ctrl Simulation Results

Simulation Results: rom_ctrl

18/01/2026 00:06:04 sha: 8ead910 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
98.54 %

code
99.55 %

assert
96.80 %

func
99.28 %

line
99.46 %

branch
99.64 %

cond
98.66 %

toggle
100.00 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		79.87%
V3		100.00%

92/92 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rom_ctrl_smoke	7.210s	588.523us	2	2	100.00
csr_hw_reset				5	5	100.00
	rom_ctrl_csr_hw_reset	7.800s	142.883us	5	5	100.00
csr_rw				20	20	100.00
	rom_ctrl_csr_rw	8.690s	580.496us	20	20	100.00
csr_bit_bash				5	5	100.00
	rom_ctrl_csr_bit_bash	6.020s	166.982us	5	5	100.00
csr_aliasing				5	5	100.00
	rom_ctrl_csr_aliasing	5.000s	300.605us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	rom_ctrl_csr_mem_rw_with_rand_reset	6.920s	150.771us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	rom_ctrl_csr_rw	8.690s	580.496us	20	20	100.00
	rom_ctrl_csr_aliasing	5.000s	300.605us	5	5	100.00
mem_walk				5	5	100.00
	rom_ctrl_mem_walk	5.850s	169.904us	5	5	100.00
mem_partial_access				5	5	100.00
	rom_ctrl_mem_partial_access	6.460s	166.348us	5	5	100.00

214/214 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_throughput_chk				2	2	100.00
	rom_ctrl_max_throughput_chk	6.170s	608.064us	2	2	100.00
stress_all				20	20	100.00
	rom_ctrl_stress_all	25.120s	1083.207us	20	20	100.00
kmac_err_chk				2	2	100.00
	rom_ctrl_kmac_err_chk	7.410s	805.673us	2	2	100.00
alert_test				50	50	100.00
	rom_ctrl_alert_test	8.810s	557.722us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	rom_ctrl_tl_errors	9.240s	172.357us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	rom_ctrl_tl_errors	9.240s	172.357us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	rom_ctrl_csr_hw_reset	7.800s	142.883us	5	5	100.00
	rom_ctrl_csr_rw	8.690s	580.496us	20	20	100.00
	rom_ctrl_csr_aliasing	5.000s	300.605us	5	5	100.00
	rom_ctrl_same_csr_outstanding	7.560s	180.518us	20	20	100.00
tl_d_partial_access				50	50	100.00
	rom_ctrl_csr_hw_reset	7.800s	142.883us	5	5	100.00
	rom_ctrl_csr_rw	8.690s	580.496us	20	20	100.00
	rom_ctrl_csr_aliasing	5.000s	300.605us	5	5	100.00
	rom_ctrl_same_csr_outstanding	7.560s	180.518us	20	20	100.00

V2S

254/318 passed

79.87 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
corrupt_sig_fatal_chk				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	130.120s	8008.594us	16	20	80.00
passthru_mem_tl_intg_err				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	27.110s	7130.910us	20	20	100.00
tl_intg_err				21	25	84.00
	rom_ctrl_sec_cm	271.720s	855.004us	1	5	20.00
	rom_ctrl_tl_intg_err	61.830s	418.435us	20	20	100.00
prim_fsm_check				1	5	20.00
	rom_ctrl_sec_cm	271.720s	855.004us	1	5	20.00
prim_count_check				1	5	20.00
	rom_ctrl_sec_cm	271.720s	855.004us	1	5	20.00
sec_cm_checker_ctr_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	130.120s	8008.594us	16	20	80.00
sec_cm_checker_ctrl_flow_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	130.120s	8008.594us	16	20	80.00
sec_cm_checker_fsm_local_esc				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	130.120s	8008.594us	16	20	80.00
sec_cm_compare_ctrl_flow_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	130.120s	8008.594us	16	20	80.00
sec_cm_compare_ctr_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	130.120s	8008.594us	16	20	80.00
sec_cm_compare_ctr_redun				1	5	20.00
	rom_ctrl_sec_cm	271.720s	855.004us	1	5	20.00
sec_cm_fsm_sparse				1	5	20.00
	rom_ctrl_sec_cm	271.720s	855.004us	1	5	20.00
sec_cm_mem_scramble				2	2	100.00
	rom_ctrl_smoke	7.210s	588.523us	2	2	100.00
sec_cm_mem_digest				2	2	100.00
	rom_ctrl_smoke	7.210s	588.523us	2	2	100.00
sec_cm_intersig_mubi				2	2	100.00
	rom_ctrl_smoke	7.210s	588.523us	2	2	100.00
sec_cm_bus_integrity				20	20	100.00
	rom_ctrl_tl_intg_err	61.830s	418.435us	20	20	100.00
sec_cm_bus_local_esc				18	22	81.82
	rom_ctrl_corrupt_sig_fatal_chk	130.120s	8008.594us	16	20	80.00
	rom_ctrl_kmac_err_chk	7.410s	805.673us	2	2	100.00
sec_cm_mux_mubi				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	130.120s	8008.594us	16	20	80.00
sec_cm_mux_consistency				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	130.120s	8008.594us	16	20	80.00
sec_cm_ctrl_redun				16	20	80.00
	rom_ctrl_corrupt_sig_fatal_chk	130.120s	8008.594us	16	20	80.00
sec_cm_ctrl_mem_integrity				20	20	100.00
	rom_ctrl_passthru_mem_tl_intg_err	27.110s	7130.910us	20	20	100.00
sec_cm_tlul_fifo_ctr_redun				1	5	20.00
	rom_ctrl_sec_cm	271.720s	855.004us	1	5	20.00

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				20	20	100.00
	rom_ctrl_stress_all_with_rand_reset	457.510s	5196.794us	20	20	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
	rom_ctrl_corrupt_sig_fatal_chk	71213194460992646496996133503688669751818131183027895998130412081338259886251	75	UVM_ERROR @ 1518625434 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 1518625434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	77598295255833775108184114393665408039652057160944199702043351470370892962467	107	UVM_ERROR @ 2204999310 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 2204999310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	89222356387934623423766900855334688540817345091943722472879270708416939941648	75	UVM_ERROR @ 182141674 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 182141674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	26946226662368524189001106600514197009790025077464730984683526318781423479231	89	UVM_ERROR @ 2451911853 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) UVM_INFO @ 2451911853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	rom_ctrl_sec_cm	15511578553906818754744807513306902312777245175245325779099422889306139737910	231	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 26997428ps failed at 26997428ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 27039095ps failed at 27039095ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
	rom_ctrl_sec_cm	72106795881770211897909800511110081503818628488635070134080370409387703822936	237	Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 33845333ps failed at 33845333ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 33845333ps failed at 33845333ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
	rom_ctrl_sec_cm	38890659014192115087618225982557916304202488942808873638558485305649055993554	483	Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 38309156ps failed at 38309156ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' Starting assertion attempts at time 40720730ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119)) Starting assertion attempts at time 40720730ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
	rom_ctrl_sec_cm	34382400005937582293521076751430466874628104078887833549354512000367034367188	547	Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 58209451ps failed at 58209451ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 58219655ps failed at 58219655ps Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'