| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
89.31% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 11.270s | 2027.883us | 2 | 2 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 17.590s | 1042.103us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| rom_ctrl_csr_rw | 10.360s | 290.773us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| rom_ctrl_csr_bit_bash | 9.530s | 212.818us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| rom_ctrl_csr_aliasing | 10.680s | 6167.909us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| rom_ctrl_csr_mem_rw_with_rand_reset | 14.990s | 4185.008us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| rom_ctrl_csr_rw | 10.360s | 290.773us | 20 | 20 | 100.00 | |
| rom_ctrl_csr_aliasing | 10.680s | 6167.909us | 5 | 5 | 100.00 | |
| mem_walk | 5 | 5 | 100.00 | |||
| rom_ctrl_mem_walk | 9.790s | 425.671us | 5 | 5 | 100.00 | |
| mem_partial_access | 5 | 5 | 100.00 | |||
| rom_ctrl_mem_partial_access | 10.090s | 291.354us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_throughput_chk | 2 | 2 | 100.00 | |||
| rom_ctrl_max_throughput_chk | 10.350s | 1104.187us | 2 | 2 | 100.00 | |
| stress_all | 20 | 20 | 100.00 | |||
| rom_ctrl_stress_all | 54.300s | 1113.286us | 20 | 20 | 100.00 | |
| kmac_err_chk | 2 | 2 | 100.00 | |||
| rom_ctrl_kmac_err_chk | 14.790s | 556.191us | 2 | 2 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| rom_ctrl_alert_test | 13.640s | 1020.131us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| rom_ctrl_tl_errors | 15.950s | 4122.124us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| rom_ctrl_tl_errors | 15.950s | 4122.124us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 17.590s | 1042.103us | 5 | 5 | 100.00 | |
| rom_ctrl_csr_rw | 10.360s | 290.773us | 20 | 20 | 100.00 | |
| rom_ctrl_csr_aliasing | 10.680s | 6167.909us | 5 | 5 | 100.00 | |
| rom_ctrl_same_csr_outstanding | 12.380s | 551.528us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 17.590s | 1042.103us | 5 | 5 | 100.00 | |
| rom_ctrl_csr_rw | 10.360s | 290.773us | 20 | 20 | 100.00 | |
| rom_ctrl_csr_aliasing | 10.680s | 6167.909us | 5 | 5 | 100.00 | |
| rom_ctrl_same_csr_outstanding | 12.380s | 551.528us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| corrupt_sig_fatal_chk | 19 | 20 | 95.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 293.520s | 16655.246us | 19 | 20 | 95.00 | |
| passthru_mem_tl_intg_err | 20 | 20 | 100.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 55.030s | 6118.990us | 20 | 20 | 100.00 | |
| tl_intg_err | 21 | 25 | 84.00 | |||
| rom_ctrl_tl_intg_err | 121.830s | 485.993us | 20 | 20 | 100.00 | |
| rom_ctrl_sec_cm | 506.820s | 790.436us | 1 | 5 | 20.00 | |
| prim_fsm_check | 1 | 5 | 20.00 | |||
| rom_ctrl_sec_cm | 506.820s | 790.436us | 1 | 5 | 20.00 | |
| prim_count_check | 1 | 5 | 20.00 | |||
| rom_ctrl_sec_cm | 506.820s | 790.436us | 1 | 5 | 20.00 | |
| sec_cm_checker_ctr_consistency | 19 | 20 | 95.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 293.520s | 16655.246us | 19 | 20 | 95.00 | |
| sec_cm_checker_ctrl_flow_consistency | 19 | 20 | 95.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 293.520s | 16655.246us | 19 | 20 | 95.00 | |
| sec_cm_checker_fsm_local_esc | 19 | 20 | 95.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 293.520s | 16655.246us | 19 | 20 | 95.00 | |
| sec_cm_compare_ctrl_flow_consistency | 19 | 20 | 95.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 293.520s | 16655.246us | 19 | 20 | 95.00 | |
| sec_cm_compare_ctr_consistency | 19 | 20 | 95.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 293.520s | 16655.246us | 19 | 20 | 95.00 | |
| sec_cm_compare_ctr_redun | 1 | 5 | 20.00 | |||
| rom_ctrl_sec_cm | 506.820s | 790.436us | 1 | 5 | 20.00 | |
| sec_cm_fsm_sparse | 1 | 5 | 20.00 | |||
| rom_ctrl_sec_cm | 506.820s | 790.436us | 1 | 5 | 20.00 | |
| sec_cm_mem_scramble | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 11.270s | 2027.883us | 2 | 2 | 100.00 | |
| sec_cm_mem_digest | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 11.270s | 2027.883us | 2 | 2 | 100.00 | |
| sec_cm_intersig_mubi | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 11.270s | 2027.883us | 2 | 2 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| rom_ctrl_tl_intg_err | 121.830s | 485.993us | 20 | 20 | 100.00 | |
| sec_cm_bus_local_esc | 21 | 22 | 95.45 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 293.520s | 16655.246us | 19 | 20 | 95.00 | |
| rom_ctrl_kmac_err_chk | 14.790s | 556.191us | 2 | 2 | 100.00 | |
| sec_cm_mux_mubi | 19 | 20 | 95.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 293.520s | 16655.246us | 19 | 20 | 95.00 | |
| sec_cm_mux_consistency | 19 | 20 | 95.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 293.520s | 16655.246us | 19 | 20 | 95.00 | |
| sec_cm_ctrl_redun | 19 | 20 | 95.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 293.520s | 16655.246us | 19 | 20 | 95.00 | |
| sec_cm_ctrl_mem_integrity | 20 | 20 | 100.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 55.030s | 6118.990us | 20 | 20 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 1 | 5 | 20.00 | |||
| rom_ctrl_sec_cm | 506.820s | 790.436us | 1 | 5 | 20.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 20 | 20 | 100.00 | |||
| rom_ctrl_stress_all_with_rand_reset | 495.530s | 11849.366us | 20 | 20 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' | ||||
| rom_ctrl_sec_cm | 92118092694275332778340101436629690833991728454629582336564771555324571808566 | 106 |
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 1405987ps failed at 1405987ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 1405987ps failed at 1405987ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
|
|
| rom_ctrl_sec_cm | 85252392900738405890333740271494942861681856902215470163664165807552852942941 | 190 |
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 13853182ps failed at 13853182ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 13853182ps failed at 13853182ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
|
|
| Offending '(curr_fwd | pend_req[d2h.d_source].pend)' | ||||
| rom_ctrl_sec_cm | 59100055022631599707332153910538141872260948229175475451850183521079641297717 | 106 |
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 1768114ps failed at 1768114ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
Starting assertion attempts at time 5247679ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
Starting assertion attempts at time 5247679ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
|
|
| Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' | ||||
| rom_ctrl_sec_cm | 74612960938150514226273306853453051912470513051481435189744183496273236805954 | 174 |
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 49845580ps failed at 49845580ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 49855681ps failed at 49855681ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
|
|
| UVM_ERROR (cip_base_vseq.sv:1015) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire | ||||
| rom_ctrl_corrupt_sig_fatal_chk | 72308647991858185735453747280798744533734399516767532297153801566834252868945 | 100 |
UVM_ERROR @ 7144252723 ps: (cip_base_vseq.sv:1015) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
UVM_INFO @ 7144252723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|