Simulation Results: spi_device

 
18/01/2026 00:06:04 sha: 8ead910 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.98 %
  • code
  • 94.28 %
  • assert
  • 94.41 %
  • func
  • 99.26 %
  • line
  • 99.17 %
  • branch
  • 98.49 %
  • cond
  • 96.65 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
99.29%
V2
99.91%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 49 50 98.00
spi_device_flash_and_tpm 398.590s 189722.047us 49 50 98.00
csr_hw_reset 5 5 100.00
spi_device_csr_hw_reset 1.140s 74.667us 5 5 100.00
csr_rw 20 20 100.00
spi_device_csr_rw 2.640s 210.751us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_device_csr_bit_bash 26.710s 13509.317us 5 5 100.00
csr_aliasing 5 5 100.00
spi_device_csr_aliasing 11.840s 3781.362us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_device_csr_mem_rw_with_rand_reset 3.020s 134.694us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_device_csr_rw 2.640s 210.751us 20 20 100.00
spi_device_csr_aliasing 11.840s 3781.362us 5 5 100.00
mem_walk 5 5 100.00
spi_device_mem_walk 0.930s 30.411us 5 5 100.00
mem_partial_access 5 5 100.00
spi_device_mem_partial_access 2.510s 751.249us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 50 50 100.00
spi_device_csb_read 1.160s 17.799us 50 50 100.00
mem_parity 20 20 100.00
spi_device_mem_parity 1.480s 32.567us 20 20 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.730s 47.871us 1 1 100.00
tpm_read 50 50 100.00
spi_device_tpm_rw 9.450s 546.862us 50 50 100.00
tpm_write 50 50 100.00
spi_device_tpm_rw 9.450s 546.862us 50 50 100.00
tpm_hw_reg 100 100 100.00
spi_device_tpm_read_hw_reg 29.870s 10552.003us 50 50 100.00
spi_device_tpm_sts_read 1.480s 117.955us 50 50 100.00
tpm_fully_random_case 50 50 100.00
spi_device_tpm_all 41.330s 7412.695us 50 50 100.00
pass_cmd_filtering 100 100 100.00
spi_device_pass_cmd_filtering 33.830s 112589.198us 50 50 100.00
spi_device_flash_all 362.440s 251648.669us 50 50 100.00
pass_addr_translation 100 100 100.00
spi_device_pass_addr_payload_swap 26.650s 37928.526us 50 50 100.00
spi_device_flash_all 362.440s 251648.669us 50 50 100.00
pass_payload_translation 100 100 100.00
spi_device_pass_addr_payload_swap 26.650s 37928.526us 50 50 100.00
spi_device_flash_all 362.440s 251648.669us 50 50 100.00
cmd_info_slots 50 50 100.00
spi_device_flash_all 362.440s 251648.669us 50 50 100.00
cmd_read_status 100 100 100.00
spi_device_intercept 29.130s 5268.422us 50 50 100.00
spi_device_flash_all 362.440s 251648.669us 50 50 100.00
cmd_read_jedec 100 100 100.00
spi_device_intercept 29.130s 5268.422us 50 50 100.00
spi_device_flash_all 362.440s 251648.669us 50 50 100.00
cmd_read_sfdp 100 100 100.00
spi_device_intercept 29.130s 5268.422us 50 50 100.00
spi_device_flash_all 362.440s 251648.669us 50 50 100.00
cmd_fast_read 100 100 100.00
spi_device_intercept 29.130s 5268.422us 50 50 100.00
spi_device_flash_all 362.440s 251648.669us 50 50 100.00
cmd_read_pipeline 100 100 100.00
spi_device_intercept 29.130s 5268.422us 50 50 100.00
spi_device_flash_all 362.440s 251648.669us 50 50 100.00
flash_cmd_upload 50 50 100.00
spi_device_upload 28.580s 23760.677us 50 50 100.00
mailbox_command 50 50 100.00
spi_device_mailbox 93.460s 40974.955us 50 50 100.00
mailbox_cross_outside_command 50 50 100.00
spi_device_mailbox 93.460s 40974.955us 50 50 100.00
mailbox_cross_inside_command 50 50 100.00
spi_device_mailbox 93.460s 40974.955us 50 50 100.00
cmd_read_buffer 99 100 99.00
spi_device_flash_mode 48.150s 5223.452us 49 50 98.00
spi_device_read_buffer_direct 24.300s 45407.636us 50 50 100.00
cmd_dummy_cycle 100 100 100.00
spi_device_mailbox 93.460s 40974.955us 50 50 100.00
spi_device_flash_all 362.440s 251648.669us 50 50 100.00
quad_spi 50 50 100.00
spi_device_flash_all 362.440s 251648.669us 50 50 100.00
dual_spi 50 50 100.00
spi_device_flash_all 362.440s 251648.669us 50 50 100.00
4b_3b_feature 50 50 100.00
spi_device_cfg_cmd 19.990s 3611.320us 50 50 100.00
write_enable_disable 50 50 100.00
spi_device_cfg_cmd 19.990s 3611.320us 50 50 100.00
TPM_with_flash_or_passthrough_mode 49 50 98.00
spi_device_flash_and_tpm 398.590s 189722.047us 49 50 98.00
tpm_and_flash_trans_with_min_inactive_time 50 50 100.00
spi_device_flash_and_tpm_min_idle 524.080s 645427.626us 50 50 100.00
stress_all 50 50 100.00
spi_device_stress_all 915.540s 503725.861us 50 50 100.00
alert_test 50 50 100.00
spi_device_alert_test 1.110s 12.884us 50 50 100.00
intr_test 50 50 100.00
spi_device_intr_test 1.030s 40.126us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_device_tl_errors 4.380s 179.048us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_device_tl_errors 4.380s 179.048us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_device_csr_hw_reset 1.140s 74.667us 5 5 100.00
spi_device_csr_rw 2.640s 210.751us 20 20 100.00
spi_device_csr_aliasing 11.840s 3781.362us 5 5 100.00
spi_device_same_csr_outstanding 3.420s 66.583us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_device_csr_hw_reset 1.140s 74.667us 5 5 100.00
spi_device_csr_rw 2.640s 210.751us 20 20 100.00
spi_device_csr_aliasing 11.840s 3781.362us 5 5 100.00
spi_device_same_csr_outstanding 3.420s 66.583us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_device_tl_intg_err 17.460s 1437.327us 20 20 100.00
spi_device_sec_cm 1.360s 1231.652us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
spi_device_tl_intg_err 17.460s 1437.327us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 50 50 100.00
spi_device_flash_mode_ignore_cmds 481.710s 175431.964us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (spi_device_scoreboard.sv:2350) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufWatermark mismatch, act (*) != exp *
spi_device_flash_mode 11750328872854812398988540749819874301360409252452728800066743582250661704301 73
UVM_ERROR @ 373591360 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
UVM_INFO @ 1194421416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp *
spi_device_flash_and_tpm 3486791987281044267489809892551579656662562206733116163411449344690073874928 106
UVM_ERROR @ 16058261338 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (15042560 [0xe58800] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0xe58800 != exp 0x0
UVM_INFO @ 18428063331 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 8/13
UVM_INFO @ 18428063331 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 9/13
tl_ul_fuzzy_flash_status_q[i] = 0xcb0200
tl_ul_fuzzy_flash_status_q[i] = 0x399a78