Simulation Results: spi_host

 
18/01/2026 00:06:04 sha: 8ead910 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.55 %
  • code
  • 95.02 %
  • assert
  • 95.21 %
  • func
  • 90.42 %
  • block
  • 96.82 %
  • line
  • 98.69 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_host_smoke 111.000s 3355.319us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_host_csr_hw_reset 2.000s 57.821us 5 5 100.00
csr_rw 20 20 100.00
spi_host_csr_rw 2.000s 27.085us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_host_csr_bit_bash 3.000s 842.158us 5 5 100.00
csr_aliasing 5 5 100.00
spi_host_csr_aliasing 2.000s 21.863us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 23.974us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_host_csr_rw 2.000s 27.085us 20 20 100.00
spi_host_csr_aliasing 2.000s 21.863us 5 5 100.00
mem_walk 5 5 100.00
spi_host_mem_walk 2.000s 16.205us 5 5 100.00
mem_partial_access 5 5 100.00
spi_host_mem_partial_access 2.000s 38.568us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 50 50 100.00
spi_host_performance 7.000s 62.653us 50 50 100.00
error_event_intr 150 150 100.00
spi_host_overflow_underflow 14.000s 383.248us 50 50 100.00
spi_host_error_cmd 3.000s 17.243us 50 50 100.00
spi_host_event 461.000s 73770.937us 50 50 100.00
clock_rate 50 50 100.00
spi_host_speed 10.000s 65.935us 50 50 100.00
speed 50 50 100.00
spi_host_speed 10.000s 65.935us 50 50 100.00
chip_select_timing 50 50 100.00
spi_host_speed 10.000s 65.935us 50 50 100.00
sw_reset 50 50 100.00
spi_host_sw_reset 480.000s 35998.108us 50 50 100.00
passthrough_mode 50 50 100.00
spi_host_passthrough_mode 3.000s 95.973us 50 50 100.00
cpol_cpha 50 50 100.00
spi_host_speed 10.000s 65.935us 50 50 100.00
full_cycle 50 50 100.00
spi_host_speed 10.000s 65.935us 50 50 100.00
duplex 50 50 100.00
spi_host_smoke 111.000s 3355.319us 50 50 100.00
tx_rx_only 50 50 100.00
spi_host_smoke 111.000s 3355.319us 50 50 100.00
stress_all 50 50 100.00
spi_host_stress_all 99.000s 19074.015us 50 50 100.00
spien 50 50 100.00
spi_host_spien 114.000s 3841.771us 50 50 100.00
stall 50 50 100.00
spi_host_status_stall 441.000s 181084.645us 50 50 100.00
Idlecsbactive 50 50 100.00
spi_host_idlecsbactive 36.000s 3210.601us 50 50 100.00
data_fifo_status 50 50 100.00
spi_host_overflow_underflow 14.000s 383.248us 50 50 100.00
alert_test 50 50 100.00
spi_host_alert_test 2.000s 24.627us 50 50 100.00
intr_test 50 50 100.00
spi_host_intr_test 2.000s 18.810us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_host_tl_errors 3.000s 89.879us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_host_tl_errors 3.000s 89.879us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 57.821us 5 5 100.00
spi_host_csr_rw 2.000s 27.085us 20 20 100.00
spi_host_csr_aliasing 2.000s 21.863us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 24.514us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 57.821us 5 5 100.00
spi_host_csr_rw 2.000s 27.085us 20 20 100.00
spi_host_csr_aliasing 2.000s 21.863us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 24.514us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_host_sec_cm 2.000s 50.421us 5 5 100.00
spi_host_tl_intg_err 2.000s 98.070us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
spi_host_tl_intg_err 2.000s 98.070us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 8 10 80.00
spi_host_upper_range_clkdiv 420.000s 200000.000us 8 10 80.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_host_upper_range_clkdiv 45184973110471643667963846278973287709511538376836714031012389406902925662113 162
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_upper_range_clkdiv 30940507681154049522889893443083571792305546675092886669586199797695117304589 129
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---