Simulation Results: sram_ctrl

 
18/01/2026 00:06:04 sha: 8ead910 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.74 %
  • code
  • 96.07 %
  • assert
  • 95.83 %
  • func
  • 98.33 %
  • line
  • 99.11 %
  • branch
  • 97.77 %
  • cond
  • 92.78 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.08%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sram_ctrl_smoke 92.030s 1348.532us 50 50 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.050s 16.863us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 1.040s 38.885us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 2.500s 120.421us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 1.060s 73.193us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 6.160s 2701.842us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 1.040s 38.885us 20 20 100.00
sram_ctrl_csr_aliasing 1.060s 73.193us 5 5 100.00
mem_walk 50 50 100.00
sram_ctrl_mem_walk 340.920s 57587.470us 50 50 100.00
mem_partial_access 50 50 100.00
sram_ctrl_mem_partial_access 176.620s 10539.619us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 50 50 100.00
sram_ctrl_multiple_keys 1454.160s 25216.535us 50 50 100.00
stress_pipeline 50 50 100.00
sram_ctrl_stress_pipeline 465.060s 21496.794us 50 50 100.00
bijection 50 50 100.00
sram_ctrl_bijection 2672.500s 1839431.653us 50 50 100.00
access_during_key_req 50 50 100.00
sram_ctrl_access_during_key_req 1032.770s 19013.082us 50 50 100.00
lc_escalation 50 50 100.00
sram_ctrl_lc_escalation 133.150s 54632.871us 50 50 100.00
executable 50 50 100.00
sram_ctrl_executable 1881.330s 103206.547us 50 50 100.00
partial_access 100 100 100.00
sram_ctrl_partial_access 88.950s 4277.346us 50 50 100.00
sram_ctrl_partial_access_b2b 565.180s 86522.958us 50 50 100.00
max_throughput 150 150 100.00
sram_ctrl_max_throughput 85.550s 4241.489us 50 50 100.00
sram_ctrl_throughput_w_partial_write 99.020s 798.158us 50 50 100.00
sram_ctrl_throughput_w_readback 97.640s 3659.664us 50 50 100.00
regwen 50 50 100.00
sram_ctrl_regwen 1163.510s 21352.713us 50 50 100.00
ram_cfg 50 50 100.00
sram_ctrl_ram_cfg 5.470s 2386.752us 50 50 100.00
stress_all 50 50 100.00
sram_ctrl_stress_all 7664.930s 155434.747us 50 50 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 1.040s 38.160us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 4.910s 725.970us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 4.910s 725.970us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.050s 16.863us 5 5 100.00
sram_ctrl_csr_rw 1.040s 38.885us 20 20 100.00
sram_ctrl_csr_aliasing 1.060s 73.193us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.190s 143.067us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.050s 16.863us 5 5 100.00
sram_ctrl_csr_rw 1.040s 38.885us 20 20 100.00
sram_ctrl_csr_aliasing 1.060s 73.193us 5 5 100.00
sram_ctrl_same_csr_outstanding 1.190s 143.067us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 68.590s 41482.396us 20 20 100.00
tl_intg_err 20 25 80.00
sram_ctrl_sec_cm 0.970s 1.435us 0 5 0.00
sram_ctrl_tl_intg_err 4.920s 756.220us 20 20 100.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 0.970s 1.435us 0 5 0.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 4.920s 756.220us 20 20 100.00
sec_cm_ctrl_config_regwen 50 50 100.00
sram_ctrl_regwen 1163.510s 21352.713us 50 50 100.00
sec_cm_readback_config_regwen 50 50 100.00
sram_ctrl_regwen 1163.510s 21352.713us 50 50 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 1.040s 38.885us 20 20 100.00
sec_cm_exec_config_mubi 50 50 100.00
sram_ctrl_executable 1881.330s 103206.547us 50 50 100.00
sec_cm_exec_intersig_mubi 50 50 100.00
sram_ctrl_executable 1881.330s 103206.547us 50 50 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 50 50 100.00
sram_ctrl_executable 1881.330s 103206.547us 50 50 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
sram_ctrl_lc_escalation 133.150s 54632.871us 50 50 100.00
sec_cm_prim_ram_ctrl_mubi 40 50 80.00
sram_ctrl_mubi_enc_err 11.060s 7377.140us 40 50 80.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 68.590s 41482.396us 20 20 100.00
sec_cm_mem_readback 36 50 72.00
sram_ctrl_readback_err 11.210s 6613.448us 36 50 72.00
sec_cm_mem_scramble 50 50 100.00
sram_ctrl_smoke 92.030s 1348.532us 50 50 100.00
sec_cm_addr_scramble 50 50 100.00
sram_ctrl_smoke 92.030s 1348.532us 50 50 100.00
sec_cm_instr_bus_lc_gated 50 50 100.00
sram_ctrl_executable 1881.330s 103206.547us 50 50 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 0.970s 1.435us 0 5 0.00
sec_cm_key_global_esc 50 50 100.00
sram_ctrl_lc_escalation 133.150s 54632.871us 50 50 100.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 0.970s 1.435us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 0.970s 1.435us 0 5 0.00
sec_cm_scramble_key_sideload 50 50 100.00
sram_ctrl_smoke 92.030s 1348.532us 50 50 100.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 0.970s 1.435us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sram_ctrl_stress_all_with_rand_reset 127.660s 5090.332us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 43418207396799348827010407120864126300334293056250839349670794102387673499041 96
UVM_ERROR @ 2602332 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 2602332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 93133136302182171963411177159688822124268669515764360170647233904847170761845 96
UVM_ERROR @ 3688705 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 3688705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_sec_cm 74469520715934189584359620256860068888542058048439255080336953212991813874981 97
UVM_ERROR @ 5184748 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 5184748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 115682580677797836108660842600637929702620197276267870010319094698683684025895 95
UVM_ERROR @ 3287997629 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x31) != exp (0xf)
UVM_INFO @ 3287997629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 50998101529489870667897370251809464230494383995487791372681272977378741698141 95
UVM_ERROR @ 2738400237 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1) != exp (0x7a)
UVM_INFO @ 2738400237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 54615973004704706282536088223127046346431692754574841904528390605962735208200 95
UVM_ERROR @ 672863085 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x20) != exp (0x48)
UVM_INFO @ 672863085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 114306483238796394185104678424352801485280892792334604197739211288913725272045 95
UVM_ERROR @ 690376166 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x16) != exp (0x34)
UVM_INFO @ 690376166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 67249586850212866844248669730929825477461894817444797635591426909958053668344 95
UVM_ERROR @ 1046296991 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2b) != exp (0x46)
UVM_INFO @ 1046296991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 40715288235495480956452571179886647296563474271760489636937905132960451347743 95
UVM_ERROR @ 1315200375 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xa) != exp (0x2d)
UVM_INFO @ 1315200375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 18326235177640909733867627737092772614469064845315453247498714373461067139554 95
UVM_ERROR @ 2627049742 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x63) != exp (0x48)
UVM_INFO @ 2627049742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 115478290768707587711003603259936780306260739446048657317785607402940608025527 95
UVM_ERROR @ 656815411 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x6c) != exp (0x19)
UVM_INFO @ 656815411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 81125703546907552867141012194565786470346972091261468974841267215405292185487 95
UVM_ERROR @ 2739371332 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2b) != exp (0x4b)
UVM_INFO @ 2739371332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 25403397827530926960146869053295584601840052569448968509904176109534962617467 95
UVM_ERROR @ 1319274425 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x23) != exp (0x22)
UVM_INFO @ 1319274425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 10080893937794460643201320946185580003464830829654265528380920296722202184521 95
UVM_ERROR @ 3129599413 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5a) != exp (0x39)
UVM_INFO @ 3129599413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 28841580636198365002640719192136987406635725264802883247456699641223243452570 95
UVM_ERROR @ 681270315 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x74) != exp (0x7e)
UVM_INFO @ 681270315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 16677063981011048644705697470096465673200574365056131467670138798584721920699 95
UVM_ERROR @ 704520113 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2) != exp (0x32)
UVM_INFO @ 704520113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_readback_err 94240179863815040390133124044291975109646304020935395403367438466036206730612 95
UVM_ERROR @ 687132147 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x67) != exp (0x26)
UVM_INFO @ 687132147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))'
sram_ctrl_sec_cm 39395121302297685106895200318890985445020722306610636165666577895437915787164 96
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 3893523 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 3893523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
sram_ctrl_mubi_enc_err 82911539622143913498159386196213887850949095391860341770752781300020193172855 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2742576185 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2742576185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 106905975551413099856519143797505837727870904602305129392411904154762635612879 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 2438952656 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 2438952656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 46608100732234092567210017063803205766887754318130164357466875264129230691743 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 662786092 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 662786092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 101911457593191814583413809430914587209941391898698627481555852387551064203843 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 1396151869 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 1396151869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 30393511483554404783341468178532896505627940858036936822086645947593188880962 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 1375832838 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 1375832838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 23812990059563367206651680566289836759799625755016963044689403761752434537955 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 3872748541 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 3872748541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 92922031290930115137275487417241572462611953584685454298328972874942250381942 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 4694140038 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 4694140038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 4976648365766360284710861152798515948451012337128932821240346475775990395081 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 696765250 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 696765250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 113377136646040609302250207580696826589128919693153531710351237788649861654075 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 691678816 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 691678816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_mubi_enc_err 84782831727196330060418396578138634577054424743186327067530134414945829628601 101
Offending 'reqfifo_rvalid'
UVM_ERROR @ 701675478 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
UVM_INFO @ 701675478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(depth_o <= *'(Depth))'
sram_ctrl_sec_cm 93542857487252211159653961404269785176017635869273677299370362506491567319409 96
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 1434745 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 1434745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---