sram_ctrl Simulation Results

Simulation Results: sram_ctrl

18/01/2026 00:06:04 sha: 8ead910 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.81 %

code
96.12 %

assert
95.79 %

func
98.52 %

line
99.07 %

branch
97.98 %

cond
92.90 %

toggle
90.66 %

FSM
100.00 %

Validation stages

V1		99.13%
V2		100.00%
V2S		93.97%
V3		100.00%

228/230 passed

99.13 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	sram_ctrl_smoke	93.650s	1729.180us	50	50	100.00
csr_hw_reset				5	5	100.00
	sram_ctrl_csr_hw_reset	0.890s	16.869us	5	5	100.00
csr_rw				20	20	100.00
	sram_ctrl_csr_rw	0.910s	46.974us	20	20	100.00
csr_bit_bash				5	5	100.00
	sram_ctrl_csr_bit_bash	1.680s	243.448us	5	5	100.00
csr_aliasing				5	5	100.00
	sram_ctrl_csr_aliasing	0.890s	39.837us	5	5	100.00
csr_mem_rw_with_rand_reset				18	20	90.00
	sram_ctrl_csr_mem_rw_with_rand_reset	2.230s	162.755us	18	20	90.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	sram_ctrl_csr_rw	0.910s	46.974us	20	20	100.00
	sram_ctrl_csr_aliasing	0.890s	39.837us	5	5	100.00
mem_walk				50	50	100.00
	sram_ctrl_mem_walk	12.670s	3127.794us	50	50	100.00
mem_partial_access				50	50	100.00
	sram_ctrl_mem_partial_access	6.670s	355.295us	50	50	100.00

890/890 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
multiple_keys				50	50	100.00
	sram_ctrl_multiple_keys	1278.280s	35385.901us	50	50	100.00
stress_pipeline				50	50	100.00
	sram_ctrl_stress_pipeline	425.330s	17679.341us	50	50	100.00
bijection				50	50	100.00
	sram_ctrl_bijection	111.910s	57496.817us	50	50	100.00
access_during_key_req				50	50	100.00
	sram_ctrl_access_during_key_req	1113.290s	13372.576us	50	50	100.00
lc_escalation				50	50	100.00
	sram_ctrl_lc_escalation	10.960s	4688.781us	50	50	100.00
executable				50	50	100.00
	sram_ctrl_executable	1521.000s	4576.495us	50	50	100.00
partial_access				100	100	100.00
	sram_ctrl_partial_access	88.910s	202.512us	50	50	100.00
	sram_ctrl_partial_access_b2b	517.700s	218493.532us	50	50	100.00
max_throughput				150	150	100.00
	sram_ctrl_max_throughput	101.370s	538.429us	50	50	100.00
	sram_ctrl_throughput_w_partial_write	91.450s	1626.038us	50	50	100.00
	sram_ctrl_throughput_w_readback	101.600s	560.866us	50	50	100.00
regwen				50	50	100.00
	sram_ctrl_regwen	1507.960s	17157.261us	50	50	100.00
ram_cfg				50	50	100.00
	sram_ctrl_ram_cfg	1.200s	32.576us	50	50	100.00
stress_all				50	50	100.00
	sram_ctrl_stress_all	3374.620s	56108.550us	50	50	100.00
alert_test				50	50	100.00
	sram_ctrl_alert_test	1.050s	43.401us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	sram_ctrl_tl_errors	3.240s	181.745us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	sram_ctrl_tl_errors	3.240s	181.745us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	sram_ctrl_csr_hw_reset	0.890s	16.869us	5	5	100.00
	sram_ctrl_csr_rw	0.910s	46.974us	20	20	100.00
	sram_ctrl_csr_aliasing	0.890s	39.837us	5	5	100.00
	sram_ctrl_same_csr_outstanding	0.980s	15.048us	20	20	100.00
tl_d_partial_access				50	50	100.00
	sram_ctrl_csr_hw_reset	0.890s	16.869us	5	5	100.00
	sram_ctrl_csr_rw	0.910s	46.974us	20	20	100.00
	sram_ctrl_csr_aliasing	0.890s	39.837us	5	5	100.00
	sram_ctrl_same_csr_outstanding	0.980s	15.048us	20	20	100.00

V2S

733/780 passed

93.97 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
passthru_mem_tl_intg_err				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	3.860s	1296.638us	20	20	100.00
tl_intg_err				20	25	80.00
	sram_ctrl_tl_intg_err	2.760s	669.556us	20	20	100.00
	sram_ctrl_sec_cm	1.020s	19.774us	0	5	0.00
prim_count_check				0	5	0.00
	sram_ctrl_sec_cm	1.020s	19.774us	0	5	0.00
sec_cm_bus_integrity				20	20	100.00
	sram_ctrl_tl_intg_err	2.760s	669.556us	20	20	100.00
sec_cm_ctrl_config_regwen				50	50	100.00
	sram_ctrl_regwen	1507.960s	17157.261us	50	50	100.00
sec_cm_readback_config_regwen				50	50	100.00
	sram_ctrl_regwen	1507.960s	17157.261us	50	50	100.00
sec_cm_exec_config_regwen				20	20	100.00
	sram_ctrl_csr_rw	0.910s	46.974us	20	20	100.00
sec_cm_exec_config_mubi				50	50	100.00
	sram_ctrl_executable	1521.000s	4576.495us	50	50	100.00
sec_cm_exec_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1521.000s	4576.495us	50	50	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				50	50	100.00
	sram_ctrl_executable	1521.000s	4576.495us	50	50	100.00
sec_cm_lc_escalate_en_intersig_mubi				50	50	100.00
	sram_ctrl_lc_escalation	10.960s	4688.781us	50	50	100.00
sec_cm_prim_ram_ctrl_mubi				46	50	92.00
	sram_ctrl_mubi_enc_err	1.780s	613.264us	46	50	92.00
sec_cm_mem_integrity				20	20	100.00
	sram_ctrl_passthru_mem_tl_intg_err	3.860s	1296.638us	20	20	100.00
sec_cm_mem_readback				37	50	74.00
	sram_ctrl_readback_err	1.750s	83.392us	37	50	74.00
sec_cm_mem_scramble				50	50	100.00
	sram_ctrl_smoke	93.650s	1729.180us	50	50	100.00
sec_cm_addr_scramble				50	50	100.00
	sram_ctrl_smoke	93.650s	1729.180us	50	50	100.00
sec_cm_instr_bus_lc_gated				50	50	100.00
	sram_ctrl_executable	1521.000s	4576.495us	50	50	100.00
sec_cm_ram_tl_lc_gate_fsm_sparse				0	5	0.00
	sram_ctrl_sec_cm	1.020s	19.774us	0	5	0.00
sec_cm_key_global_esc				50	50	100.00
	sram_ctrl_lc_escalation	10.960s	4688.781us	50	50	100.00
sec_cm_key_local_esc				0	5	0.00
	sram_ctrl_sec_cm	1.020s	19.774us	0	5	0.00
sec_cm_init_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	1.020s	19.774us	0	5	0.00
sec_cm_scramble_key_sideload				50	50	100.00
	sram_ctrl_smoke	93.650s	1729.180us	50	50	100.00
sec_cm_tlul_fifo_ctr_redun				0	5	0.00
	sram_ctrl_sec_cm	1.020s	19.774us	0	5	0.00

50/50 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				50	50	100.00
	sram_ctrl_stress_all_with_rand_reset	695.780s	1830.961us	50	50	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value:
	sram_ctrl_csr_mem_rw_with_rand_reset	43759793848163099706189967891420370134399277403527444765050594240428376551412	95	UVM_ERROR @ 63351893 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (11 [0xb] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9 UVM_INFO @ 63351893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_csr_mem_rw_with_rand_reset	68046473276057726356380927686204473093476768942850336803924719860925502318511	95	UVM_ERROR @ 47910108 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (8 [0x8] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9 UVM_INFO @ 47910108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: sram_ctrl_regs_reg_block.status.init_error reset value:
	sram_ctrl_sec_cm	19139096701733010736961142723403690601801526705119917589689172312336385137431	100	UVM_ERROR @ 19774486 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 19774486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	41333338852649678236369695037042672834357568890693225027296879112444887416041	97	UVM_ERROR @ 5949769 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 5949769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_sec_cm	111770930258094272255383128019557360629631055395293633455005584537944762666919	96	UVM_ERROR @ 1839253 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 1839253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act () != exp ()
	sram_ctrl_readback_err	103771899339596262382173084795296976409147937607444724371365921594481428751996	95	UVM_ERROR @ 125458989 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3d) != exp (0x17) UVM_INFO @ 125458989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	65839962725562824079103624300342508382944861250677105137081691570625400554312	95	UVM_ERROR @ 100539190 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x13) != exp (0x74) UVM_INFO @ 100539190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	40491069631656943860388545156400237531142180092692580555007103189333177569396	95	UVM_ERROR @ 45936427 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0xe) != exp (0x42) UVM_INFO @ 45936427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	399798300167899977321555018584704492017402024048056973530854593273461452159	95	UVM_ERROR @ 117329645 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x37) != exp (0x18) UVM_INFO @ 117329645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	19858870110251894339555907216702335430004984995257476290920275400499694461188	95	UVM_ERROR @ 97571429 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x66) != exp (0x7e) UVM_INFO @ 97571429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	97527168217486752463378498349009312135408888517143293442699045152668633415592	95	UVM_ERROR @ 68005662 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x7c) != exp (0x1a) UVM_INFO @ 68005662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	48678033779234360001522935993705642026735695154546878427006821727598661758185	95	UVM_ERROR @ 108380469 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x72) != exp (0x5d) UVM_INFO @ 108380469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	27407191632356347597873402200984596474124886585629131859844594170750226406528	95	UVM_ERROR @ 99767215 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x59) != exp (0x40) UVM_INFO @ 99767215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	64569673351331528692310593936122880632954556114221843450786044665831088667422	95	UVM_ERROR @ 87179976 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x27) != exp (0x4) UVM_INFO @ 87179976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	73262119822616045196064742925694466961627257336732994724961453173432658869510	95	UVM_ERROR @ 99806395 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x69) != exp (0x1d) UVM_INFO @ 99806395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	73603218895053477939297979397198358623455084857073001741292208984390335574927	95	UVM_ERROR @ 97012295 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x59) != exp (0x45) UVM_INFO @ 97012295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	81714132754846540519376048042703339308958666891239474394830900362944106118504	95	UVM_ERROR @ 28629083 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x68) != exp (0x36) UVM_INFO @ 28629083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_readback_err	74764312281873246016170248502178571403926723529876936553735907192757928232241	95	UVM_ERROR @ 115325398 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3c) != exp (0x53) UVM_INFO @ 115325398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	sram_ctrl_sec_cm	105161193438052573203033735820814685509825840287059580755670087317754251450975	97	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 4079276ps failed at 4079276ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 4119276ps failed at 4119276ps Offending '(curr_fwd \| pend_req[d2h.d_source].pend)'
	sram_ctrl_sec_cm	63385958364049564233912064209505392420069234251519517487893577517847796926141	98	Offending '(curr_fwd \| pend_req[d2h.d_source].pend)' UVM_ERROR @ 3434515 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0 UVM_INFO @ 3434515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending 'reqfifo_rvalid'
	sram_ctrl_mubi_enc_err	97794195022401520140273972089278582135322353425605400773619396638671451230797	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 33268582 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 33268582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	57472184168656775126731449811556848733065942851856124810931918432036125380019	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 53225641 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 53225641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	31672677623693358386927754492401248354426908238498227240573442955838229824335	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 138142879 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 138142879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	sram_ctrl_mubi_enc_err	91206959146770465604284725986134590247003856185317011949400890450900999780943	101	Offending 'reqfifo_rvalid' UVM_ERROR @ 99810566 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty UVM_INFO @ 99810566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---