Simulation Results: adc_ctrl

 
25/01/2026 00:05:59 sha: d6c1f63 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.45 %
  • code
  • 98.74 %
  • assert
  • 95.95 %
  • func
  • 91.66 %
  • line
  • 99.05 %
  • branch
  • 98.64 %
  • cond
  • 96.03 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
adc_ctrl_smoke 20.790s 6078.161us 50 50 100.00
csr_hw_reset 5 5 100.00
adc_ctrl_csr_hw_reset 3.430s 1342.817us 5 5 100.00
csr_rw 20 20 100.00
adc_ctrl_csr_rw 2.140s 354.676us 20 20 100.00
csr_bit_bash 5 5 100.00
adc_ctrl_csr_bit_bash 26.750s 15975.839us 5 5 100.00
csr_aliasing 5 5 100.00
adc_ctrl_csr_aliasing 4.860s 1119.138us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.950s 586.098us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
adc_ctrl_csr_rw 2.140s 354.676us 20 20 100.00
adc_ctrl_csr_aliasing 4.860s 1119.138us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 50 50 100.00
adc_ctrl_filters_polled 1124.330s 492088.293us 50 50 100.00
filters_polled_fixed 50 50 100.00
adc_ctrl_filters_polled_fixed 1098.100s 486969.968us 50 50 100.00
filters_interrupt 48 50 96.00
adc_ctrl_filters_interrupt 1173.120s 490423.922us 48 50 96.00
filters_interrupt_fixed 50 50 100.00
adc_ctrl_filters_interrupt_fixed 1030.140s 493521.820us 50 50 100.00
filters_wakeup 50 50 100.00
adc_ctrl_filters_wakeup 1528.050s 577501.662us 50 50 100.00
filters_wakeup_fixed 50 50 100.00
adc_ctrl_filters_wakeup_fixed 1336.530s 613574.902us 50 50 100.00
filters_both 48 50 96.00
adc_ctrl_filters_both 1327.340s 568682.336us 48 50 96.00
clock_gating 39 50 78.00
adc_ctrl_clock_gating 1006.140s 2000000.000us 39 50 78.00
poweron_counter 50 50 100.00
adc_ctrl_poweron_counter 19.110s 5434.233us 50 50 100.00
lowpower_counter 50 50 100.00
adc_ctrl_lowpower_counter 118.470s 38665.076us 50 50 100.00
fsm_reset 50 50 100.00
adc_ctrl_fsm_reset 411.480s 129609.230us 50 50 100.00
stress_all 47 50 94.00
adc_ctrl_stress_all 2807.890s 1260559.986us 47 50 94.00
alert_test 50 50 100.00
adc_ctrl_alert_test 2.500s 513.954us 50 50 100.00
intr_test 50 50 100.00
adc_ctrl_intr_test 1.860s 337.749us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
adc_ctrl_tl_errors 3.430s 386.424us 20 20 100.00
tl_d_illegal_access 20 20 100.00
adc_ctrl_tl_errors 3.430s 386.424us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
adc_ctrl_csr_hw_reset 3.430s 1342.817us 5 5 100.00
adc_ctrl_csr_rw 2.140s 354.676us 20 20 100.00
adc_ctrl_csr_aliasing 4.860s 1119.138us 5 5 100.00
adc_ctrl_same_csr_outstanding 19.130s 4462.336us 20 20 100.00
tl_d_partial_access 50 50 100.00
adc_ctrl_csr_hw_reset 3.430s 1342.817us 5 5 100.00
adc_ctrl_csr_rw 2.140s 354.676us 20 20 100.00
adc_ctrl_csr_aliasing 4.860s 1119.138us 5 5 100.00
adc_ctrl_same_csr_outstanding 19.130s 4462.336us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
adc_ctrl_tl_intg_err 17.510s 8005.403us 20 20 100.00
adc_ctrl_sec_cm 16.270s 7850.572us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
adc_ctrl_tl_intg_err 17.510s 8005.403us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
adc_ctrl_stress_all_with_rand_reset 24.810s 17898.894us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
adc_ctrl_clock_gating 97606066276506123955923635941831187641578527600197830126190337808365064700563 318
UVM_ERROR @ 3837595636 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 3837595636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 102483294512263415845047178785704053121699696908163466636672246548401627891714 318
UVM_ERROR @ 4967432522 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 4967432522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 40839962839563751616693613717195609659473153205130350856409573746430353829767 385
UVM_ERROR @ 495180080811 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 495180080811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 35573501962746863927196346030274807495233702169931293749310732307194621781992 335
UVM_ERROR @ 183987551761 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 183987551761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 54554330663669429899689778586318035486962226470084491728143223878493055113305 318
UVM_ERROR @ 2329611538 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 2329611538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 47373261899531779957390176053948038288075615190456767356211208506830583096241 462
UVM_ERROR @ 298926590640 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_INFO @ 298926590640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
adc_ctrl_stress_all 111286323844971584172164803636027203787616510203374991774112402612773603704729 319
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 110875820573689787966918801263589309811374559073309478675154752036207339100557 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 21544013760253418589143121344103904416966928860339803561156228202329519074576 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 56311840287788808023340779423101975477874509634010336009592173827914993088121 350
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 97242071181054852528686479838478488377313900373675600135096265912542637157514 350
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 57301664529616483527387196336233363088827993541064748243753353233693967563171 352
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 14513474325183010052627047913063170785066555946998019176619034345592832490244 335
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 9368282430877322007751328468766442274850928215848667428227982693415765215591 318
UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state
adc_ctrl_filters_interrupt 32440991698830547319980611129818981141372318749432665221145428038757047951224 318
UVM_ERROR @ 83578140692 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 83578140692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 88020166829340812577150035022070544614154591388320563251721139915659773838906 318
UVM_ERROR @ 161620231013 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 161620231013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 89553604051656199907558539461320946956675368888687493145990309142742812357594 318
UVM_ERROR @ 85387876415 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 85387876415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 61491818587860421095452782966467231836117389407526805255767094628741779297008 334
UVM_ERROR @ 246166786011 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
UVM_INFO @ 246166786011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---